4.2 Issue 2 - MDIO Ethernet PHY Communications.............................................................................................................. 61
4.3 Issue 3 - DC Barrel Jack Warning when Hot-Plugging.....................................................................................................61
5 References............................................................................................................................................................................ 61
6 Revision History................................................................................................................................................................... 61
List of Figures
Figure 3-1. Top View of the AM64x/AM243x GP EVM Board......................................................................................................5
Figure 3-2. Bottom View of the AM64x/AM243x GP EVM Board................................................................................................ 6
Figure 3-3. General Processor Board Functional Block Diagram................................................................................................8
Figure 3-4. AM64x/AM243x GP EVM Clock Tree...................................................................................................................... 11
Figure 3-5. Overall Reset Architecture of the AM64x/AM243x GP EVM................................................................................... 12
Figure 3-6. Power Good LEDs...................................................................................................................................................15
Figure 3-7. Power ON and OFF Sequencing.............................................................................................................................16
Figure 3-8. AM64x/AM243x Core Supply and Array Core Supply Options............................................................................... 17
Figure 3-9. AM64x/AM243x GP EVM Schematic Excerpt, Boot Mode Selection Switches (SW2, SW3)................................. 19
Figure 3-10. AM64x/AM243x GP EVP PCB, Boot Mode Selection Switches (SW2, SW3).......................................................19
Figure 3-11. JTAG Interface.......................................................................................................................................................23
Figure 3-12. Test Automation Header........................................................................................................................................26
Figure 3-13. AM64x/AM243xUART Interfaces...........................................................................................................................28
Figure 3-14. AM64x/AM243x DDR4 Interface........................................................................................................................... 29
Figure 3-15. Micro SD Interface.................................................................................................................................................30
Figure 3-16. eMMC Interface.....................................................................................................................................................31
Figure 3-17. AM64x/AM243x OSPI Interface............................................................................................................................ 32
Figure 3-18. Ethernet Interface - CPSW Domain...................................................................................................................... 33
Figure 3-19. Ethernet Interface - ICSSG Domain...................................................................................................................... 34
Figure 3-20. AM64x/AM243xEthernet Interfaces - CPSW Ethernet Strap Settings.................................................................. 39
Figure 3-21. AM64x/AM243x Ethernet Interfaces - ICSSG1 Ethernet Strap Settings............................................................... 40
Figure 3-22. AM64x/AM243x Ethernet Interfaces - ICSSG2 Ethernet Strap Settings............................................................... 41
Figure 3-23. AM64x/AM243x GP EVM Ethernet Interface LED................................................................................................ 42
Figure 3-24. AM64x/AM243x USB 2.0 Host Interface............................................................................................................... 44
Figure 3-25. AM64x/AM243x PCIe Interface............................................................................................................................. 45
Figure 3-26. AM64x/AM243x High Speed Expansion Connector..............................................................................................52
Figure 3-27. AM64x/AM243x High Speed Expansion Connector - Part 1................................................................................. 53
Figure 3-28. AM64x/AM243x High Speed Expansion Connector - Part 2................................................................................. 54
Figure 3-29. AM64x/AM243x CAN Interfaces............................................................................................................................55
Figure 3-30. AM64x/AM243x I2C Interfaces and Address Assignment of Peripherals............................................................. 57
Figure 3-31. AM64x/AM243x FSI Interface............................................................................................................................... 58
Figure 4-1. AM64x/AM243x GP EVM Modification Label Location........................................................................................... 59
Figure 4-2. XDS110 CCS Connection Error Dialog................................................................................................................... 60
Figure 4-3. XDS110 debug reset utility command-line function.................................................................................................60
List of Tables
Table 1-1. AM64x/AM243x GP EVM PCB design revisions, and asssembly variants.................................................................4
Table 3-1. Source Clock Selection for the Clock Buffer............................................................................................................. 11
Table 3-2. VMAIN LED...............................................................................................................................................................13
Table 3-3. INA Devices I2C Slave Address............................................................................................................................... 13
Table 3-4. Power Test Points..................................................................................................................................................... 14
Table 3-5. Power LEDs.............................................................................................................................................................. 15
Table 3-6. SoC Power Supply....................................................................................................................................................18
Table 3-7. BOOTMODE Bits...................................................................................................................................................... 20
Table 3-8. PLL Reference Clock Selection BOOTMODE[2:0]................................................................................................... 20
Table 3-9. Boot Device Selection BOOTMODE[6:3]..................................................................................................................20
Table 3-10. Primary Boot Media Configuration BOOTMODE[9:7]............................................................................................. 21
Table 3-11. Backup Boot Mode Selection BOOTMODE[12:10]................................................................................................. 21
Table 3-12. Backup Boot Media Configuration BOOTMODE[13].............................................................................................. 21
Table 3-13. Selection of HSE Connector and JTAG TRACE Functionality................................................................................ 22
Table 3-14. TI20 Pin Connector (J25) Pin-Out...........................................................................................................................22
Table 3-15. TI 60-Pin Connector (J33) Pin-Out......................................................................................................................... 24
Table 3-16. List of Signals Routed to Test Automation Header................................................................................................. 25
Table 3-17. Test Automation Header (J38) Pin-out....................................................................................................................27
Table 3-18. Board ID Memory Header Information.................................................................................................................... 32
Table 3-19. Default Strap Setting of CPSW Ethernet PHY........................................................................................................ 36
Table of Contents
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2 AM64x/AM243x GP EVM User's Guide SPRUIX0C – FEBRUARY 2021 – REVISED JUNE 2021
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