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3.4.8.2.2 eMMC Interface

The processor card supports eMMC Flash memory (part number Micron MTFC16GAPALBH-IT), connected to

MMC0 port of the AM64x processor. The flash is connected to 8 bits of the MMC0 interface supporting HS400

double data rates up to 200 MHz.

Figure 3-16. eMMC Interface

3.4.8.3 OSPI Interface

The GP EVM has 512 Mbit OSPI memory device of part number S28HS512TGABHM010 from Cypress is

connected to OSPI0 interface of AM64x/AM243x SoC. The OSPI interface supports single and double data rates

with memory speed up to 200 MBps SDR and 400 MBps DDR (200 MHz clock speed).

Two signals are routed to OSPI0_DQS:

1. OSPI0_DQS from the memory device

2. OSPI0_LBCLK from SoC

To route DQS from memory device: Mount R601 and R592 and DNI R600 and R591.

To route OSPI0_LBCLK from SoC: Mount R600 and R591 and DNI R601 and R592

Note

For more information, see the OSPI and QSPI Board Design and Layout Guidelines section in the

AM64x Sitara™ Processors Data Manual.

OSPI and QSPI implementation: 0 Ω resistors are provided for DATA[7:0], DQS, INT# and CLK signals.

Footprints to mount external pull up resistors are provided on DATA[7:0] to prevent bus floating. The

footprint for the OSPI memory also allows the installation of either a QSPI memory or an OSPI memory.

S25FL256SABHI200 from Cypress should be used in variants where QSPI flash is required. The 0 ohm resistors

used in pins OSPI_DATA[4:7] will be removed if QSPI flash is mounted

Note

For QSPI Configuration

Remove 0E resistors from the following

1. OSPI_DQ4 to OSPI_DQ7 nets (R432, R441, R442, R443)

2. OSPI_INTn (R158)

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System Description

SPRUIX0C – FEBRUARY 2021 – REVISED JUNE 2021

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AM64x/AM243x GP EVM User's Guide 31

Texas Instruments AM64 Series User Manual

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