Texas Instruments C28 Series Student Guide

C28x CPU
TMS320C28x Internal Bussing
As with many DSP type devices, multiple busses are used to move data between the memories
and peripherals and the CPU. The C28x memory bus architecture contains:
• A program read bus (22 bit address line and 32 bit data line)
• A data read bus (32 bit address line and 32 bit data line)
• A data write bus (32 bit address line and 32 bit data line)
C28x Internal Bus Structure
C28x Internal Bus Structure
Data
Data
-
-
write Address Bus (32)
write Address Bus (32)
Program Address Bus (22)
Program Address Bus (22)
Execution
Execution
R
R
-
-
M
M
-
-
W
W
Atomic
Atomic
ALU
ALU
Real
Real
-
-
Time
Time
Emulation
Emulation
&
&
Test
Test
Engine
Engine
Program
Program
-
-
read Data Bus (32)
read Data Bus (32)
JTAG
JTAG
Program
Program
Decoder
Decoder
PC
PC
XAR0
XAR0
to
to
XAR7
XAR7
SP
SP
DP
DP
@X
@X
ARAU
ARAU
MPY32x32
MPY32x32
XT
XT
P
P
ACC
ACC
ALU
ALU
Registers
Registers
Debug
Debug
Register Bus / Result Bus
Register Bus / Result Bus
Data/Program
Data/Program
-
-
write Data Bus (32)
write Data Bus (32)
Data
Data
-
-
read Address Bus (32)
read Address Bus (32)
Data
Data
-
-
read Data Bus (32)
read Data Bus (32)
Memory
Memory
Data
Data
(4G * 16)
(4G * 16)
Program
Program
(4M* 16)
(4M* 16)
Standard
Standard
Peripherals
Peripherals
External
External
Interfaces
Interfaces
The 32-bit-wide data busses enable single cycle 32-bit operations. This multiple bus architecture,
known as a Harvard Bus Architecture enables the C28x to fetch an instruction, read a data value
and write a data value in a single cycle. All peripherals and memories are attached to the memory
bus and will prioritize memory accesses.
1 - 6 C28x - Architecture Overview

Texas Instruments C28 Series Specifications

General

Brand	Texas Instruments
Model	C28 Series
Category	Computer Hardware
Language	English