Analog-to-Digital Converter
ADC Module
ADC Module
12
12
-
-
bit resolution ADC core
bit resolution ADC core
Sixteen analog inputs (range of 0 to 3V)
Sixteen analog inputs (range of 0 to 3V)
Two analog input multiplexers
Two analog input multiplexers
Up to 8 analog input channels each
Up to 8 analog input channels each
Two sample/hold units (for each input
Two sample/hold units (for each input
mux
mux
)
)
Sequential and simultaneous sampling modes
Sequential and simultaneous sampling modes
Autosequencing
Autosequencing
capability
capability
-
-
up to 16
up to 16
autoconversions
autoconversions
Two independent 8
Two independent 8
-
-
state sequencers
state sequencers
“Dual
“Dual
-
-
sequencer mode”
sequencer mode”
“Cascaded mode”
“Cascaded mode”
Sixteen individually addressable result registers
Sixteen individually addressable result registers
Multiple trigger sources for start
Multiple trigger sources for start
-
-
of
of
-
-
conversion
conversion
External trigger, S/W, and Event Manager events
External trigger, S/W, and Event Manager events
F2812 ADC Clocking Example
F2812 ADC Clocking Example
CLKIN
CLKIN
(30 MHz)
(30 MHz)
HSPCLK
HSPCLK
(150 MHz)
(150 MHz)
ADCCLKPS
bits
ADCTRL3
ADCTRL3
0011b
0011b
FCLK
FCLK
(25 MHz)
(25 MHz)
FCLK = HSPCLK/(2*ADCCLKPS)
FCLK = HSPCLK/(2*ADCCLKPS)
ADCCLK =
ADCCLK =
FCLK/(CPS+1)
FCLK/(CPS+1)
ADCCLK
ADCCLK
(25 MHz)
(25 MHz)
CPS bit
ADCTRL1
ADCTRL1
0b
To ADC
To ADC
pipeline
pipeline
sampling
sampling
window
window
ACQ_PS
bits
ADCTRL1
ADCTRL1
0111b
Important: ADCCLK can be a maximum of 25 MHz!
Important: ADCCLK can be a maximum of 25 MHz!
SYSCLKOUT
SYSCLKOUT
(150 MHz)
(150 MHz)
PLLCR
PLLCR
DIV
bits
1010b
To CPU
To CPU
sampling window = (ACQ_PS + 1)*(1/ADCCLK)
sampling window = (ACQ_PS + 1)*(1/ADCCLK)
PCLKCR.ADCENCLK = 1
PCLKCR.ADCENCLK = 1
HISPCP
HISPCP
HSPCLK
bits
000b
6 - 4 C28x - Analog-to-Digital Converter
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