Multi-Channel Buffered Serial Port (McBSP)
Multi-Channel Buffered Serial Port (McBSP)
McBSP Block Diagram
16
TX FIFO_15
TX FIFO_0
DXR2 TX Buffer
XSR2
16
TX FIFO_15
TX FIFO_0
DXR1 TX Buffer
XSR1
16
RX FIFO_15
RX FIFO_0
DRR2 RX Buffer
RBR2 Register
16
RX FIFO_15
RX FIFO_0
DRR1 RX Buffer
RBR1 Register
16
RSR2
16
RSR1
DX
DR
FSX
FSR
CLKX
CLKR
Definition: Bit and Word
CLK
b7 b6 b5 b4 b3 b2 b1 b0
Word
FS
a1 a0
Bit
D
“Word” or “channel” contains
number of bits (8, 12, 16, 20, 24, 32)
“Bit” - one data bit per SP clock period
C28x - Communications 11 - 17