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General-Purpose Timers

General

Purpose Timer Block Diagram

(EVA)

Bit Timer

Counter

TxCMPR

. 15

GPTCONA

GPTCONATxCNT

TxCNT

. 15

Compare

Logic

Clock

Prescaler

Output

Logic

TPS 2

TxCON

. 10

Period

Shadowed

Compare

Shadowed

TxPR

. 15

External

Internal

(HSPCLK)

TCLKS 1

TxCON

. 5

TxPWM

TxCMP

Note: x = 1 or 2

QEP

The TxPR period register holds the user specified counting period. TxPR is automatically loaded

from the period register buffer on a counter underflow, which is defined as TxCNT=0. This

allows for on-the-fly timer period changes. Note that the period register buffer is static in that if

no change in the current period value is desired, one is not required to write the same value to the

buffer on successive timer cycles.

The clocking signal for each GP Timer can be individually selected as either the internal CPU

clock, or the external TCLKINA/B pin. In addition, the QEP outputs can be selected for clocking

GP Timers. The external TDIRA/B pin is used to determine the counting direction only when the

timer is in the directional-up/down counting mode. The prescale counter is used to divide the

clocking signal down to the desired frequency, when necessary.

Each GP Timer has its own set of interrupts, all of which are individually maskable:

1. TxPINT - period match interrupt. Flag is set when the timer counter matches the value in

the timer period register.

2. TxUFINT - underflow interrupt. Flag is set when the timer counter becomes zero.

3. TxOFINT - overflow interrupt. Flag is set when the timer counter matches 0FFFFh.

Note: Maximum frequency for External or QEP is CLKIN/4

C28x - Event Manager 7 - 9

Brand	Texas Instruments
Model	C28 Series
Category	Computer Hardware
Language	English

Texas Instruments C28 Series Student Guide

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