External Interface (XINTF)
F2812 XINTF Timings
F2812 XINTF Timings
Five external zones: 0, 1, 2, 6, 7
Five external zones: 0, 1, 2, 6, 7
Each zone has separate read and write timings
Each zone has separate read and write timings
XREADY signal can be used to extend ACTIVE phase
XREADY signal can be used to extend ACTIVE phase
Read Timing
Read Timing
XZCS
XZCS
XRD
XRD
XA[18:0]
XA[18:0]
XD[15:0]
XD[15:0]
valid address
valid address
valid data
valid data
XRDLEAD
XRDLEAD
XRDACTIVE
XRDACTIVE
XRDTRAIL
XRDTRAIL
DSP latches data
DSP latches data
SRAM
SRAM
ta(A)
ta(A)
XINTF Clocking
XINTF Clocking
Specify read timing and write timing separately, for
Specify read timing and write timing separately, for
each zone:
each zone:
1
1
0
0
/2
/2
XTIMING0
XTIMING0
XTIMING1
XTIMING1
XTIMING2
XTIMING2
XTIMING6
XTIMING6
XTIMING7
XTIMING7
XBANK
XBANK
Lead/Active/Trail
Lead/Active/Trail
1
1
0
0
/2
/2
XCLKOUT
XCLKOUT
XTIMCLK
XTIMCLK
SYSCLKOUT
SYSCLKOUT
C28x
C28x
CPU
CPU
•
•
•
•
•
•
XINTCNF2
XINTCNF2
(XTIMCLK bit)
(XTIMCLK bit)
XINTCNF2
XINTCNF2
(CLKMODE bit)
(CLKMODE bit)
Lead:
Lead:
0
0
-
-
3 XTIMCLK Cycles
3 XTIMCLK Cycles
Active:
Active:
1
1
-
-
7 XTIMCLK Cycles
7 XTIMCLK Cycles
Trail:
Trail:
0
0
-
-
3 XTIMCLK Cycles
3 XTIMCLK Cycles
XINTCNF2
XINTCNF2
(CLKOFF bit)
(CLKOFF bit)
Each zone has a X2TIMING bit that can double the
Each zone has a X2TIMING bit that can double the
timing values (both read and write affected)
timing values (both read and write affected)
10 - 8 C28x - System Design
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