Table 6-3. Signal Descriptions (continued)
FUNCTION
SIGNAL
NAME
PIN NO.
(1)
PIN TYPE
(2)
DESCRIPTION
64 PM
48 PT,
RGZ
32
RHB
28
DGS28
SPI
SPI0_CS0
27
42
54
8
16
6
12
9 I/O SPI0 chip-select 0
SPI0_CS1
23
28
43
58
9
20
42
7 10 I/O SPI0 chip-select 1
SPI0_CS2
19
25
59
21
41
44
28 27 I/O SPI0 chip-select 2
SPI0_CS3
2
23
24
24
42
43
27 26 I/O SPI0 chip-select 3
SPI0_SCK
5
15
46
57
12
19
27
37
10
15
16
13
16
I/O
SPI0 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI0_POCI
6
16
44
56
10
18
28
38
8
14
17
11
15
I/O SPI0 controller in/peripheral out
SPI0_PICO
7
14
45
55
11
17
29
36
9
13
18
12
14
17
I/O SPI0 controller out/peripheral in
SPI1_CS0
19
30
42
58
8
20
41
46
6
30
1
9
I/O SPI1 chip-select 0
SPI1_CS1
14
29
31
36
47
31 2 I/O SPI1 chip-select 1
SPI1_CS2
8
15
47
30
37
19 18 I/O SPI1 chip-select 2
SPI1_CS3
2
26
48
24
45
29 28 I/O SPI1 chip-select 3
SPI1_SCK
4
10
22
61
23
26
32
21 20 I/O
SPI1 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI1_POCI
2
9
20
59
21
24
31
20 19 I/O SPI1 controller in/peripheral out
SPI1_PICO
3
11
21
60
22
25
33
22 21 I/O SPI1 controller out/peripheral in
System NRST 38 4 3 6 I Reset input active low
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SLASEX6A – FEBRUARY 2023 – REVISED JUNE 2023
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