Texas Instruments RM46L852 - Page 157

PRODUCTPREVIEW
SPICLK
(clock polarity=0)
SPICSn
8
SPICLK
(clock polarity=1)
SPIENAn
9
SPISOMI
SPICLK
(clockpolarity=1)
SPICLK
(clockpolarity=0)
3
2
1
5
4
7
SPISIMOData
MustBeValid
SPISOMIDataIsValid
666
SPISIMO
RM46L852
www.ti.com SPNS185 –SEPTEMBER 2012
Figure 5-18. SPI Slave Mode External Timing (CLOCK PHASE = 0)
Figure 5-19. SPI Slave Mode Enable Timing (CLOCK PHASE = 0)
Copyright © 2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 157
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