RM46L852
www.ti.com
SPNS185 –SEPTEMBER 2012
Table 4-21. Device Memory Map (continued)
FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO
FRAME CHIP FRAME ACTUA
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE L SIZE
START END
FRAME
Wrap around for accesses to
unimplemented address offsets lower
MIBADC1 RAM 8kB
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
Look-Up Table for ADC1 wrapper.
PCS[31] 0xFF3E_0000 0xFF3F_FFFF 128kB
Starts at address offset 0x2000 and
MibADC1 Look- ends at address offset 0x217F. Wrap
384B
Up Table around for accesses between offsets
0x0180 and 0x3FFF. Abort generated
for accesses beyond offset 0x4000.
Wrap around for accesses to
unimplemented address offsets lower
N2HET2 RAM PCS[34] 0xFF44_0000 0xFF45_FFFF 128kB 16kB
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
Wrap around for accesses to
unimplemented address offsets lower
N2HET1 RAM PCS[35] 0xFF46_0000 0xFF47_FFFF 128kB 16kB
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
N2HET2 TU2
PCS[38] 0xFF4C_0000 0xFF4D_FFFF 128kB 1kB Abort
RAM
N2HET1 TU1
PCS[39] 0xFF4E_0000 0xFF4F_FFFF 128kB 1kB Abort
RAM
Debug Components
CoreSight Debug Reads return zeros, writes have no
CSCS0 0xFFA0_0000 0xFFA0_0FFF 4kB 4kB
ROM effect
Cortex-R4F Reads return zeros, writes have no
CSCS1 0xFFA0_1000 0xFFA0_1FFF 4kB 4kB
Debug effect
POM CSCS4 0xFFA0_4000 0xFFA0_4FFF 4kB 4kB Abort
Peripheral Control Registers
Reads return zeros, writes have no
HTU1 PS[22] 0xFFF7_A400 0xFFF7_A4FF 256B 256B
effect
Reads return zeros, writes have no
HTU2 PS[22] 0xFFF7_A500 0xFFF7_A5FF 256B 256B
effect
Reads return zeros, writes have no
N2HET1 PS[17] 0xFFF7_B800 0xFFF7_B8FF 256B 256B
effect
Reads return zeros, writes have no
N2HET2 PS[17] 0xFFF7_B900 0xFFF7_B9FF 256B 256B
effect
Reads return zeros, writes have no
GIO PS[16] 0xFFF7_BC00 0xFFF7_BDFF 512B 256B
effect
Reads return zeros, writes have no
MIBADC1 PS[15] 0xFFF7_C000 0xFFF7_C1FF 512B 512B
effect
Reads return zeros, writes have no
MIBADC2 PS[15] 0xFFF7_C200 0xFFF7_C3FF 512B 512B
effect
Reads return zeros, writes have no
I2C PS[10] 0xFFF7_D400 0xFFF7_D4FF 256B 256B
effect
Reads return zeros, writes have no
DCAN1 PS[8] 0xFFF7_DC00 0xFFF7_DDFF 512B 512B
effect
Reads return zeros, writes have no
DCAN2 PS[8] 0xFFF7_DE00 0xFFF7_DFFF 512B 512B
effect
Reads return zeros, writes have no
DCAN3 PS[7] 0xFFF7_E000 0xFFF7_E1FF 512B 512B
effect
Reads return zeros, writes have no
LIN PS[6] 0xFFF7_E400 0xFFF7_E4FF 256B 256B
effect
Reads return zeros, writes have no
SCI PS[6] 0xFFF7_E500 0xFFF7_E5FF 256B 256B
effect
Copyright © 2012, Texas Instruments Incorporated System Information and Electrical Specifications 77
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