RM46L852
SPNS185 –SEPTEMBER 2012
www.ti.com
Table 4-21. Device Memory Map (continued)
FRAME ADDRESS RANGE RESPNSE FOR ACCESS TO
FRAME CHIP FRAME ACTUA
MODULE NAME UNIMPLEMENTED LOCATIONS IN
SELECT SIZE L SIZE
START END
FRAME
W2FC (USB
device controller 0xFCF7_8A00 0xFCF7_8A7F 128B 128B Abort
registers)
OHCI (USB Host
controller 0xFCF7_8B00 0xFCF7_8BFF 256B 256B Abort
registers)
EMIF Registers 0xFCFF_E800 0xFCFF_E8FF 256B 256B Abort
SCR5: Enhanced Timer Peripherals
ePWM1 0xFCF7_8C00 0xFCF7_8CFF 256B 256B Abort
ePWM2 0xFCF7_8D00 0xFCF7_8DFF 256B 256B Abort
ePWM3 0xFCF7_8E00 0xFCF7_8EFF 256B 256B Abort
ePWM4 0xFCF7_8F00 0xFCF7_8FFF 256B 256B Abort
ePWM5 0xFCF7_9000 0xFCF7_90FF 256B 256B Abort
ePWM6 0xFCF7_9100 0xFCF7_91FF 256B 256B Abort
ePWM7 0xFCF7_9200 0xFCF7_92FF 256B 256B Abort
eCAP1 0xFCF7_9300 0xFCF7_94FF 256B 256B Abort
eCAP2 0xFCF7_9400 0xFCF7_95FF 256B 256B Abort
eCAP3 0xFCF7_9500 0xFCF7_96FF 256B 256B Abort
eCAP4 0xFCF7_9600 0xFCF7_97FF 256B 256B Abort
eCAP5 0xFCF7_9700 0xFCF7_98FF 256B 256B Abort
eCAP6 0xFCF7_9800 0xFCF7_99FF 256B 256B Abort
eQEP1 0xFCF7_9900 0xFCF7_9AFF 256B 256B Abort
eQEP2 0xFCF7_9A00 0xFCF7_9BFF 256B 256B Abort
Cyclic Redundancy Checker (CRC) Module Registers
CRC CRC frame 0xFE00_0000 0xFEFF_FFFF 16MB 512B Accesses above 0x200 generate abort.
Peripheral Memories
MIBSPI5 RAM PCS[5] 0xFF0A_0000 0xFF0B_FFFF 128kB 2kB Abort for accesses above 2kB
MIBSPI3 RAM PCS[6] 0xFF0C_0000 0xFF0D_FFFF 128kB 2kB Abort for accesses above 2kB
MIBSPI1 RAM PCS[7] 0xFF0E_0000 0xFF0F_FFFF 128kB 2kB Abort for accesses above 2kB
Wrap around for accesses to
unimplemented address offsets lower
DCAN3 RAM PCS[13] 0xFF1A_0000 0xFF1B_FFFF 128kB 2kB
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
DCAN2 RAM PCS[14] 0xFF1C_0000 0xFF1D_FFFF 128kB 2kB
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
DCAN1 RAM PCS[15] 0xFF1E_0000 0xFF1F_FFFF 128kB 2kB
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
MIBADC2 RAM 8kB
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
Look-Up Table for ADC2 wrapper.
PCS[29] 0xFF3A_0000 0xFF3B_FFFF 128kB
Starts at address offset 0x2000 and
MIBADC2 Look- ends at address offset 0x217F. Wrap
384B
Up Table around for accesses between offsets
0x0180 and 0x3FFF. Abort generated
for accesses beyond offset 0x4000.
76 System Information and Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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