RM46L852
SPNS185 –SEPTEMBER 2012
www.ti.com
Table 4-31. EMIF Synchronous Memory Switching Characteristics (continued)
NO. Parameter MIN MAX Unit
8 t
oh(CLKH-AIV)
Output hold time, EMIF_CLK rising to 1 ns
EMIFADDR[12:0] and EMIFBA[1:0]
invalid
9 t
d(CLKH-DV)
Delay time, EMIF_CLK rising to 7 ns
EMIFDATA[15:0] valid
10 t
oh(CLKH-DIV)
Output hold time, EMIF_CLK rising to 1 ns
EMIFDATA[15:0] invalid
11 t
d(CLKH-RASV)
Delay time, EMIF_CLK rising to 7 ns
EMIFnRAS valid
12 t
oh(CLKH-RASIV)
Output hold time, EMIF_CLK rising to 1 ns
EMIFnRAS invalid
13 t
d(CLKH-CASV)
Delay time, EMIF_CLK rising to 7 ns
EMIFnCAS valid
14 t
oh(CLKH-CASIV)
Output hold time, EMIF_CLK rising to 1 ns
EMIFnCAS invalid
15 t
d(CLKH-WEV)
Delay time, EMIF_CLK rising to 7 ns
EMIFnWE valid
16 t
oh(CLKH-WEIV)
Output hold time, EMIF_CLK rising to 1 ns
EMIFnWE invalid
17 t
dis(CLKH-DHZ)
Delay time, EMIF_CLK rising to 7 ns
EMIFDATA[15:0] tri-stated
18 t
ena(CLKH-DLZ)
Output hold time, EMIF_CLK rising to 1 ns
EMIFDATA[15:0] driving
94 System Information and Electrical Specifications Copyright © 2012, Texas Instruments Incorporated
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