Texas Instruments TMS320C6748 User Manual

158
TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017 www.ti.com
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Peripheral Information and Electrical Specifications Copyright © 2009–2017, Texas Instruments Incorporated
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(5) Use whichever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
Table 6-63. Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V]
(1) (2)
(see Figure 6-34)
NO. PARAMETER
1.3V, 1.2V 1.1V
UNIT
MIN MAX MIN MAX
1 t
d(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
0.5 16.5 1.5 18 ns
2 t
c(CKRX)
Cycle time, CLKR/X CLKR/X int 2P or 20
(3)(4)(5)
2P or 25
(3)(4) (5)
ns
3 t
w(CKRX)
Pulse duration, CLKR/X high or
CLKR/X low
CLKR/X int C - 2
(6)
C + 2
(6)
C - 2
(6)
C + 2
(6)
ns
4 t
d(CKRH-FRV)
Delay time, CLKR high to internal
FSR valid
CLKR int -4 6.5 -4 13
ns
CLKR ext 1 16.5 1 18
9 t
d(CKXH-FXV)
Delay time, CLKX high to internal
FSX valid
CLKX int -4 6.5 -4 13
ns
CLKX ext 1 16.5 1 18
12 t
dis(CKXH-DXHZ)
Disable time, DX high impedance
following last data bit from CLKX
high
CLKX int -4 6.5 -4 13
ns
CLKX ext -2 16.5 -2 18
13 t
d(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int -4 + D1
(7)
6.5 + D2
(7)
-4 + D1
(7)
13 + D2
(7)
ns
CLKX ext 1 + D1
(7)
16.5 + D2
(7)
1 + D1
(7)
18 + D2
(7)
14 t
d(FXH-DXV)
Delay time, FSX high to DX valid FSX int -4
(8)
6.5
(8)
-4
(8)
13
(8)
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext -2
(8)
16.5
(8)
-2
(8)
18
(9)

Texas Instruments TMS320C6748 Specifications

General

Brand	Texas Instruments
Model	TMS320C6748
Category	Control Unit
Language	English