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TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Peripheral Information and Electrical Specifications Copyright © 2009–2017, Texas Instruments Incorporated
6.16 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• External shift clock or an internal, programmable frequency shift clock for data transfer
• Transmit & Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it
more tolerant to DMA latency
If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must
always be set to a value of 1 or greater.
6.16.1 McBSP Peripheral Register Description(s)
Table 6-56. McBSP/FIFO Registers
McBSP0
BYTE ADDRESS
McBSP1
BYTE ADDRESS
ACRONYM REGISTER DESCRIPTION
McBSP Registers
0x01D1 0000 0x01D1 1000 DRR McBSP Data Receive Register (read-only)
0x01D1 0004 0x01D1 1004 DXR McBSP Data Transmit Register
0x01D1 0008 0x01D1 1008 SPCR McBSP Serial Port Control Register
0x01D1 000C 0x01D1 100C RCR McBSP Receive Control Register
0x01D1 0010 0x01D1 1010 XCR McBSP Transmit Control Register
0x01D1 0014 0x01D1 1014 SRGR McBSP Sample Rate Generator register
0x01D1 0018 0x01D1 1018 MCR McBSP Multichannel Control Register
0x01D1 001C 0x01D1 101C RCERE0 McBSP Enhanced Receive Channel Enable Register 0 Partition A/B
0x01D1 0020 0x01D1 1020 XCERE0 McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B
0x01D1 0024 0x01D1 1024 PCR McBSP Pin Control Register
0x01D1 0028 0x01D1 1028 RCERE1 McBSP Enhanced Receive Channel Enable Register 1 Partition C/D
0x01D1 002C 0x01D1 102C XCERE1 McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D
0x01D1 0030 0x01D1 1030 RCERE2 McBSP Enhanced Receive Channel Enable Register 2 Partition E/F
0x01D1 0034 0x01D1 1034 XCERE2 McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F
0x01D1 0038 0x01D1 1038 RCERE3 McBSP Enhanced Receive Channel Enable Register 3 Partition G/H
0x01D1 003C 0x01D1 103C XCERE3 McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H
McBSP FIFO Control and Status Registers
0x01D1 0800 0x01D1 1800 BFIFOREV BFIFO Revision Identification Register
0x01D1 0810 0x01D1 1810 WFIFOCTL Write FIFO Control Register
0x01D1 0814 0x01D1 1814 WFIFOSTS Write FIFO Status Register
0x01D1 0818 0x01D1 1818 RFIFOCTL Read FIFO Control Register
0x01D1 081C 0x01D1 181C RFIFOSTS Read FIFO Status Register
McBSP FIFO Data Registers
0x01F1 0000 0x01F1 1000 RBUF McBSP FIFO Receive Buffer
0x01F1 0000 0x01F1 1000 XBUF McBSP FIFO Transmit Buffer
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