Texas Instruments TMS320C6748 User Manual

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TMS320C6748
www.ti.com SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Peripheral Information and Electrical SpecificationsCopyright © 2009–2017, Texas Instruments Incorporated
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
6.34 Emulation Logic
The debug capabilities and features for DSP are as shown below.
DSP:
• Basic Debug
– Execution Control
– System Visibility
• Real-Time Debug
– Interrupts serviced while halted
– Low/non-intrusive system visibility while running
• Advanced Debug
– Global Start
– Global Stop
– Specify targeted memory level(s) during memory accesses
– HSRTDX (High Speed Real Time Data eXchange)
• Advanced System Control
– Subsystem reset via debug
– Peripheral notification of debug events
– Cache-coherent debug accesses
• Analysis Actions
– Stop program execution
– Generate debug interrupt
– Benchmarking with counters
– External trigger generation
– Debug state machine state transition
– Combinational and Sequential event generation
• Analysis Events
– Program event detection
– Data event detection
– External trigger Detection
– System event detection (i.e. cache miss)
– Debug state machine state detection
• Analysis Configuration
– Application access
– Debugger access
Table 6-142. DSP Debug Features
Category Hardware Feature Availability
Basic Debug
Software breakpoint Unlimited
Hardware breakpoint
Up to 10 HWBPs, including:
4 precise
(1)
HWBPs inside DSP core and one of them is associated with a counter.
2 imprecise
(1)
HWBPs from AET.
4 imprecise
(1)
HWBPs from AET which are shared for watch point.

Texas Instruments TMS320C6748 Specifications

General

Brand	Texas Instruments
Model	TMS320C6748
Category	Control Unit
Language	English