Texas Instruments TMS320C6748 - Page 201

1
MII_TCLK(Input)
MII_TXD[3]-MII_TXD[0],
MII_TXEN(Outputs)
MII_RXCLK(Input)
1
2
MII_RXD[3]-MII_RXD[0],
MII_RXDV,MII_RXER(Inputs)
201
TMS320C6748
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(1) Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER.
Table 6-100. Timing Requirements for EMAC MII Receive 10/100 Mbit/s
(1)
(see Figure 6-49)
NO.
1.3V, 1.2V, 1.1V,
1.0V
UNIT
MIN MAX
1 t
su(MRXD-MII_RXCLKH)
Setup time, receive selected signals valid before MII_RXCLK high 8 ns
2 t
h(MII_RXCLKH-MRXD)
Hold time, receive selected signals valid after MII_RXCLK high 8 ns
(1) Transmit selected signals include: MTXD3-MTXD0, and MII_TXEN.
Figure 6-49. EMAC Receive Interface Timing
Table 6-101. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s
(1)
(see Figure 6-50)
NO. PARAMETER
1.3V, 1.2V,
1.1V
1.0V
UNIT
MIN MAX MIN MAX
1
t
d(MII_TXCLKH-
MTXD)
Delay time, MII_TXCLK high to transmit selected signals valid 2 25 2 32 ns
Figure 6-50. EMAC Transmit Interface Timing