UHPI_HCS
UHPI_HAS
(D)
UHPI_HCNTL[1:0]
UHPI_HR/W
UHPI_HHWIL
UHPI_HSTROBE
(A)(C)
UHPI_HD[15:0]
(output)
UHPI_HRDY
(B)
1
2
1
2
1
2
5
6
3
4
3
1
2
1
2
1
2
8
14
15
14
8
7
1st Half-Word
2nd Half-Word
6
13
15
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1
XOR HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY
may or may not occur.
C. UHPI_HCS
reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or
UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.
D The diagram above assumes UHPI_HAS
has been pulled high.
224
TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Peripheral Information and Electrical Specifications Copyright © 2009–2017, Texas Instruments Incorporated
Figure 6-67. UHPI Read Timing (HAS Not Used, Tied High)
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