Texas Instruments TMS320C6748 - Page 51

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TMS320C6748
www.ti.com SPRS590G –JUNE 2009–REVISED JANUARY 2017
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Device ComparisonCopyright © 2009–2017, Texas Instruments Incorporated
Table 3-22. Ethernet Media Access Controller (EMAC) Terminal Functions (continued)
SIGNAL
TYPE
(1)
PULL
(2)
POWER
GROUP
(3)
DESCRIPTION
NAME NO.
RMII
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] /
RMII_MHZ_50_CLK / PRU0_R31[23]
W18 I/O CP[26] C EMAC 50-MHz clock input or output
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER /
PRU0_R31[24]
W17 I CP[26] C EMAC RMII receiver error
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0]
/ PRU0_R31[25]
V17 I CP[26] C
EMAC RMII receive data
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1]
/PRU0_R31[26]
W16 I CP[26] C
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV /
PRU1_R31[29]
W19 I CP[26] C EMAC RMII carrier sense data valid
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN /
PRU0_R31[27]
R14 O CP[26] C EMAC RMII transmit enable
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0]
/ PRU0_R31[28]
V16 O CP[26] C
EMAC RMII transmit data
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1]
/ PRU0_R31[29]
U18 O CP[26] C
MDIO
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO /
TM64P1_IN12
D17 I/O CP[10] A MDIO serial data
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDCLK /
TM64P0_IN12
E16 O CP[10] A MDIO clock