Texas Instruments TMS320C6748 - Page 58

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TMS320C6748
SPRS590G –JUNE 2009–REVISED JANUARY 2017 www.ti.com
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Device Comparison Copyright © 2009–2017, Texas Instruments Incorporated
Table 3-27. Universal Parallel Port (uPP) Terminal Functions (continued)
SIGNAL
TYPE
(1)
PULL
(2)
POWER
GROUP
(3)
DESCRIPTION
NAME NO.
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] /
PRU1_R31[15]
U2 I/O CP[28] C
uPP data bus
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] /
PRU1_R31[14]
U1 I/O CP[28] C
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] /
PRU1_R31[13]
V3 I/O CP[28] C
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] /
PRU1_R31[12]
V2 I/O CP[28] C
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] /
PRU1_R31[11]
V1 I/O CP[28] C
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] /
PRU1_R31[10]
W3 I/O CP[28] C
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9] W2 I/O CP[28] C
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8] W1 I/O CP[28] C
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7] P4 I/O CP[29] C
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6] R3 I/O CP[29] C
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5] R2 I/O CP[29] C
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4] R1 I/O CP[29] C
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3] T3 I/O CP[29] C
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2] T2 I/O CP[29] C
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1] T1 I/O CP[29] C
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0] U3 I/O CP[29] C
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] /
PRU0_R31[29]
U18 I/O CP[26] C
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] /
PRU0_R31[28]
V16 I/O CP[26] C
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN /
PRU0_R31[27]
R14 I/O CP[26] C
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] /
PRU0_R31[26]
W16 I/O CP[26] C
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0] /
PRU0_R31[25]
V17 I/O CP[26] C
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER /
PRU0_R31[24]
W17 I/O CP[26] C
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK /
PRU0_R31[23]
W18 I/O CP[26] C
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV /
PRU1_R31[29]
W19 I/O CP[26] C
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7]/PRU0_R30[15] /
PRU0_R31[15]
V18 I/O CP[27] C
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6]/ PRU0_R30[14] /
PRU0_R31[14]
V19 I/O CP[27] C
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] /PRU0_R30[13] /
PRU0_R31[13]
U19 I/O CP[27] C
VP_DIN[12] / UHPI_HD[4] / UPP_D[4]/ PRU0_R30[12] /
PRU0_R31[12]
T16 I/O CP[27] C
VP_DIN[11] / UHPI_HD[3] / UPP_D[3]/ PRU0_R30[11] /
PRU0_R31[11]
R18 I/O CP[27] C
VP_DIN[10] / UHPI_HD[2] / UPP_D[2]/ PRU0_R30[10] /
PRU0_R31[10]
R19 I/O CP[27] C
VP_DIN[9] / UHPI_HD[1] / UPP_D[1]/ PRU0_R30[9] /
PRU0_R31[9]
R15 I/O CP[27] C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0] P17 I/O CP[27] C