INIT
BOOT BIST
SAFE
RECOVERY
FSM
PFSM
STANDBY
INIT Complete
No Errors
No Residual Voltage
BOOT BIST
Error
BOOT BIST
Success
Recovery Count
Threshold
LP_STANDBY
ACTIVE
LP_STANDBY_SEL=1
MCU Power Error
Immediate Shutdown
Orderly Shutdown
A
Trigger NSLEEP2 NSLEEP1
1 1
B 1 0
C 0 1
D 0 0
WKUP1 or
Valid On Request and
STARTUP_DEST[1:0] = 11b
Off Request
C or
D
A or WKUP1 or
Valid On Request
STARTUP_DEST[1:0] = 11b
OFF Request
Warm Reset triggered by
WD_ERROR,
ESM_MCU_ERROR,
or ESM_SOC_ERROR
Retention
DDR
From any PFSM State
Valid Wake
Request
MCU
DDR
B
A or WKUP1 or
Valid On Request
STARTUP_DEST[1:0] = 11b
OFF Request
Pwr SoC Error
DDR
SOC Power Error
WKUP2 or
Valid On Request
STARTUP_DEST[1:0] = 10b
B
C or
D
B or WKUP2 or
Valid On Request
STARTUP_DEST[1:0] = 10b
OFF Request
GPIO
GPIO
GPIO
Figure 6-1. Pre-Configurable Finite State Machine (PFSM) Mission States and Transitions
When the PMICs transition from the FSM to the PFSM, several initialization instructions are performed to disable
the residual voltage checks on both the BUCK and LDO regulators. Additionally, the FIRST_STARTUP_DONE
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUCJ9 – FEBRUARY 2023
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