3.2 Control Mapping
Figure 3-2 shows the digital control signal mapping between processor and PMIC devices. For the three PMIC
devices to work together, the PMICs must establish an SPMI communication channel. The SPMI allows the
two TPS6594-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM) so that they operate as
one PFSM across all power and digital resources. The GPIO_5 and GPIO_6 pins on the TPS6594-Q1 and the
GPIO_8 and GPIO_9 pins of the LP8764-Q1 are assigned for this functionality.
Other digital connections from the PMICs to the processor provide error monitoring, processor reset, processor
wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals in order to
ensure proper operation during low power modes when only a few GPIO pins remain operational.
The digital connections shown in TPS6594-Q1 Digital Connections allow system features including 'MCU-only,
MCU Safety Island' and DDR Retention modes, functional safety up to ASIL-D, and compliant dual voltage SD
card operation.
www.ti.com Processor Connections
SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
7
Copyright © 2023 Texas Instruments Incorporated
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