7.1.2 MCU ONLY
Transitioning to the MCU ONLY state from the ACTIVE state, requires configuring the I2C_7 trigger before
changing the NSLEEP bits. The configuration must be consistent between both PMICs.
Write 0x48:0x85:0x80:0x7F // Set I2C_7 Triggers on TPS65941120
Write 0x4C:0x85:0x80:0x7F // Set I2C_7 Triggers on TPS65941421
Write 0x48:0x86:0x02:0xFC // Set NSLEEP2 to trigger TO_MCU power sequence
Instead of writing to the NSLEEP bits to return to the ACTIVE state, it is also possible to use the WKUP1 pin
on GPIO4 to return the PMIC to the ACTIVE state. Because of the similarity this is shown in the context of the
RETENTION state.
7.1.3 RETENTION
As shown in Section 6.3.9, the MCU is powered off and therefore the transition out of the RETENTION to the
MCU ONLY or the ACTIVE states must be configured before entering RETENTION. Similar to the MCU ONLY
state the I2C_7 triggers must be set for both TPS6594-Q1 PMICs. In this example GPIO4 on the TPS65941120
is used to wake the device from RETENTION to ACTIVE.
Write 0x48:0x85:0x80:0x7F // I2C_7 is high
Write 0x4C:0x85:0x80:0x7F
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0x64:0x08:0xF7 // clear interrupt of gpio4, write to clear
Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge
Write 0x48:0x86:0x00:0xFC // trigger the TO_RETENTION power sequence
After the GPIO4 has gone low and the PMICs have returned to the ACTIVE state
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 // clear interrupt of gpio4
Write 0x4C:0x3D:0x00:0xFD // clear PMICB:GPIO2, DDR_RET
In this example the TPS65941120 RTC Timer is used to wake the device from RETENTION to ACTIVE.
Write 0x48:0x85:0x80:0x7F // I2C_7 is high
Write 0x4C:0x85:0x80:0x7F
Write 0x48:0xC3:0x01;0xFE // Enable Crystal
Write 0x48:0xC5:0x05:0xF8 // minute timer, enable TIMER interrupts
Write 0x48:0xC2:0x01:0xFE // start timer, if the timer values are non-zero clear before starting
Write 0x48:0x86:0x00:0xFC // trigger the TO_RETENTION power sequence
After the RTC Timer interrupt has occurred and the PMICs have returned to the ACTIVE state
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0xC5:0x00:0xFB // disable timer interrupt, clear bit 2
Write 0x48:0xC4:0x00:0xDF // clear timer interrupt, clear bit 5
7.2 Entering and Exiting Standby
STANDBY can be entered from the ACTIVE or the RETENTION states. In order to stay in the mission state of
STANDBY and not enter the hardware state LP_STANDBY the LP_STANDBY_SEL bit must be cleared.
Similar to the RETENTION state, the STANDBY state turns off all regulators that power the processor. The
ACTIVE state is the only destination state available that the STANDBY state returns to.
When the ENABLE pin goes low, the TO_STANDBY sequence is triggered. When the ENABLE pin goes
high again, the PMICs return to the ACTIVE state, defined in the STARTUP_DEST bits. The TO_STANDBY
sequence is also triggered by the I2C_0 trigger. When triggered from I2C_0 the PMIC can be triggered to return
to the ACTIVE states by GPIO4, GPIO10, or and RTC timer or alarm. In this example, I2C_0 trigger is used to
enter the STANDBY state and the GPIO4 is used to enter the ACTIVE state.
Write 0x48:0xC3:0x00:0xF7 // LP_STANDBY_SEL=0
Write 0x48:0x7D:0xC0:0x3F // Mask NSLEEP bits
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge
Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger TO_STANDBY sequence
After the GPIO4 has gone low and the PMICs have returned to the ACTIVE state
www.ti.com Application Examples
SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
51
Copyright © 2023 Texas Instruments Incorporated
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