4.1 Achieving ASIL-B System Requirements
To achieve a system functional safety level of ASIL-B, the following PDN features are available:
• PMIC over voltage and under voltage monitoring on the power resource voltage outputs
• Watchdog monitoring of safety processor
• MCU error monitoring
• MCU reset
• I
2
C communication
• Error indicator, EN_DRV, for driving external circuitry (optional)
• Read-back of EN_DRV pin
The PDN has an in-line, external power FET, as shown in Figure 3-1, between the input supply and PMICs.
The voltage before and after the FET is monitored by the PMIC, and the PMIC controls the FET through the
OVPGDRV pin. The FET can quickly isolate the PMICs when an over-voltage event greater than 6 V is detected
on the input supply to protect the system from being damaged. This system protection includes all power rails
sourced from the FET. Any power connected upstream from the FET is not protected from over voltage events.
In Figure 3-1 the load switches that supply power to the MCU and Main I/O domains, the discrete LDO supplying
the DDR, and the discrete LDO supplying EFUSE are all connected after the FET to extend the over voltage
protection to these processor domains and discrete power resources.
The PMIC internal over voltage and under voltage monitoring and their respective monitoring threshold levels
are enabled by default and can be updated through I
2
C after startup. PMIC power rails connected directly to
the processor are monitored by default. The unused feedback pin of BUCK3 on TPS65941120-Q1, FB_B3, is
assigned to monitor the MCU IO supply voltage, VDD_MCUIO_3V3. For monitoring other supplies, the unused
feedback pins of the LP876411B5- Q1 (FB_B3 or FB_B4) are assigned to monitor the DDR supply voltage,
VDD1_DDR_1V8 and the SoC IO supply voltage, VDD_IO_3V3.
The internal Q&A Watchdog is enabled on the primary TPS6594-Q1 device. Once the device is in ACTIVE
state, the trigger or Q&A watchdog settings can be configured through the secondary I
2
C in the device. The
primary and secondary I
2
C CRC is not enabled by default but must be enabled with the I2C_2 trigger described
in section Table-6-1. Once enabled the secondary I
2
C is disabled for 2ms. It is recommended to enable I
2
C
CRC and wait a minimum of 2ms before starting the Q&A Watchdog. The steps for configuring and starting
the watchdog can be found in the TPS6594-Q1 data sheet. Setting the DISABLE_WDOG signal high on
primary TPS6594-Q1 GPIO_8 disables the watchdog timer if this feature needs to be suspended during initial
development or is not required in the system. An example of re-purposing GPIO_8 is provided in Section 7.4.
GPIO_7 of the primary TPS6594-Q1 PMIC is configured as the MCU error signal monitor, and must be enabled
though the ESM_MCU_EN register bit. MCU reset is supported through the connection between the primary
PMIC nRSTOUT pin and the MCU_PORz of the processor. Lastly, there are two I2C ports between the
TPS6594-Q1 and the processor. The first is used for all non-watchdog communication, such as voltage level
control, and the second allows the watchdog monitoring to be on an independent communication channel.
There is an option to use the EN_DRV of the primary TPS6594-Q1 PMIC to indicate an error has been detected
and the system is entering SAFE state. This signal can be utilized if the system has external circuitry that needs
to be driven by an error event. In this PDN, the EN_DRV is not utilized, but available if needed.
4.2 Achieving up to ASIL-D System Requirements
For ASIL-C or ASIL-D systems, the following features in addition to the ones described in Section 4.1 can be
used:
• PMIC over-voltage monitoring and protection on the input to the PMIC (VCCA)
• PMIC current monitoring on all output power rails
• SoC error monitoring
• Switch short-to-ground detection on BUCK regulator pins (SW_Bx)
• Residual Voltage Monitoring
• Read-back of Logic Output Pins
– nINT of all PMICs
– nRSTOUT and nRSTOUT_SOC of the primary PMIC
Supporting Functional Safety Systems www.ti.com
12 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
SLVUCJ9 – FEBRUARY 2023
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