The current monitoring is enabled by default for all BUCKs and LDOs for the TPS6594-Q1 and LP8764-Q1
devices.
GPIO_3 of the primary TPS6594-Q1 PMIC is configured as the SoC error signal monitor. Similar to the MCU
error signal monitor, this feature is enabled through I
2
C using the ESM_SOC_EN register bit. The SoC reset
functionality is supported through the connection of GPIO_11 on the primary TPS6594-Q1, configured as
nRSTOUT_SoC, to the PORz pin of the processor.
Table 4-1. System Level Safety Features
ASIL-B ASIL-D
Safety
Monitoring
Processor
External SW
Wdog
INTn
Safety MCU
Processing
ESM
Safety MCU
Reset
Safety Status
Signal with IO
Read-Back
feature
System Input
Voltage
Monitoring
SoC Main
Processing
ESM
IO Read-Back
Feature
SoC: MCU
Island
R5 Cores
PMICA: Q&A
Watchdog and
I2C2
PMICA
(1)
and
PMICB
(2)
: nINT
PMICA:
nERR_MCU
connected to
SOC:MCU_SAF
ETY_ERRz
PMICA:
nRSTOUT
connected to
MCU_PORz_1
V8
PMICA: ENDRV PMICA:
VSYS_SENSE
-OV with Safety
FET OVPGDRV
PMICA, PMICB
and PMICC with
VCCA OV & UV
and SoC
(VMON1) -UV
PMICA:
nERR_SoC
connected to
SOC:
SOC_SAFETY_
ERRz
PMICA: nINT,
nRSTOUT,
nRSTOUT_SO
C
PMICB: nINT
PMICC: nINT
(1) PMICA = TPS65941120-Q1
(2) PMICB = TPS65941421-Q1
Table 4-2. Power Monitoring Safety Features
ASIL-B ASIL-D Adds
Device Power Resource PDN Power Rail Safe State Power
Group
(1)
Supply Voltage
Monitoring
Supply Current
Monitoring
Residual Voltage
Monitoring
TPS65941120-Q1
(PMIC-A)
BUCK1-4 VDD_CPU_AVS SOC PMIC-A - OV &
UV
PMIC-A -CM PMIC-A -RVM
BUCK5 VDD_MCU_0V85 MCU PMIC-A - OV &
UV
PMIC-A -CM PMIC-A -RVM
LDO1 VDD_MCUWK_0V
8
MCU PMIC-A - OV &
UV
PMIC-A -CM
(2)
PMIC-A -RVM
(2)
LDO2 VDD_MCU_GPIO
RET_3V3
MCU PMIC-A - OV &
UV
PMIC-A -CM PMIC-A -RVM
LDO3 VDD_MCUIO_1V8 MCU PMIC-A - OV &
UV
PMIC-A -CM PMIC-A -RVM
LDO4 VDA_MCU_1V8 MCU PMIC-A - OV &
UV
PMIC-A -CM PMIC-A -RVM
www.ti.com Supporting Functional Safety Systems
SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
13
Copyright © 2023 Texas Instruments Incorporated
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