3 Processor Connections
This section details how the dual TPS6594-Q1 and LP8764-Q1 power resources and GPIO signals are
connected to the processor and other peripheral components.
3.1 Power Mapping
Figure 3-1 shows the power mapping between the dual TPS6594-Q1 PMIC and LP8764-Q1 PMIC power
resources and processor voltage domains required to support independent MCU and Main power rails. In this
configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there is a protection
FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the
input supply to the PMICs.
For SD card dual-voltage I/O support (3.3 V and 1.8 V), the TLV7103318-Q1 device can be used. A processor
GPIO control signal with a logic high default value is used to set SD VIO to 3.3 V initially. During processor
power up, the boot loader SW can set GPIO signal low to select 1.8 V level as needed for high-speed card
operation per SD specification. The GPIO allows control of the TLV7103318-Q1 voltage without the need for the
MCU processor to establish I2C communication with the PMICs during boot from SD card operations.
This PDN uses six discrete power components with three being required and three are optional depending
upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply OV
protected 3.3 V to processor I/O domains. Two load switches are required in order to enable isolation between
MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The unused
feedback pin, FB_B3, of the TPS65941120-Q1 has been configured per NVM settings, Table 5-3, to provide
voltage monitoring for VDD_MCUIO_3V3_LS power rail. The unused feedback pin, FB_B4 of the LP876411B5-
Q1 has been configured per NVM settings, Table 5-3, to provide voltage monitoring for VDD_IO_3V3 power
rail. The FB_B4 feedback pin enables all of the necessary processor power supply inputs to have voltage
monitoring coverage as needed for functional safety ASIL-B and higher systems. The third discrete device is
a TLV73318P-Q1 LDO which supplies the LPDDR4 SDRAM component with required 1.8V supply, which is
monitored by the unused feedback pin, FB_B3, of the LP876411B5-Q1. The fourth discrete power component
is an optional TLV73333-Q1 LDO that can be used for USB support. The fifth discrete power component is an
optional TLV77103318-Q1 LDO for SD power. The sixth discrete component is TLV73318P-Q1 LDO that can be
used if an end product uses a high security processor type and desires the capability to program Efuse values
on-board. If this feature is not desired, then this LDO can be omitted and processor pins terminated per data
manual recommendations.
Note
The PMIC voltage monitors on unused FB_Bx must be connected to the voltages shown in the power
map. The VMON_ABIST_EN=1 for all the PMICs. If the proper voltage is not connected to the FB_Bx
when the monitor is enabled then the self-test fails, the BIST_FAIL_INT interrupt is set, and the device
goes to the hardware SAFE RECOVERY state, see Figure 6-1, and main processor voltages are
disabled.
Processor Connections www.ti.com
4 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
SLVUCJ9 – FEBRUARY 2023
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