Write 0x48:0x7D:0x00:0x3F // unmask NSLEEP bits
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
7.3 Entering and Exiting LP_STANDBY
Entering the LP_STANDBY hardware state is the same as entering STANDBY. Exiting LP_STANDBY is
different and requires different initializations before entering LP_STANDBY. Also, when the PMICs return from
LP_STANDBY the PFSM triggers are gated by the ENABLE_INT while in STANDBY the triggers were gated by
the GPIO interrupt.
Write 0x48:0xC3:0x08:0xF7 // LP_STANDBY_SEL=1
Write 0x48:0x7D:0xC0:0x3F // Mask NSLEEP bits
Write 0x48:0x34:0xC0;0x3F // Set GPIO4 to WKUP1 (goes to ACTIVE state)
Write 0x48:0xC3:0x60;0x9F // Set the STARTUP_DEST=ACTIVE
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x4F:0x00:0xF7 // unmask interrupt for GPIO4 falling edge
Write 0x48:0x85:0x01:0xFE // set I2C_0 trigger, trigger TO_STANDBY sequence
After the GPIO4 has gone low and the PMICs have returned to the ACTIVE state
Write 0x48:0x7D:0x00:0x3F // unmask NSLEEP bits
Write 0x48:0x86:0x03:0xFC // Set NSLEEPx bits for ACTIVE state
Write 0x48:0x64:0x08:0xF7 // clear interrupt of GPIO4
Write 0x48:0x65:0x02:0xFD // clear ENABLE_INT
7.4 Runtime Customization
The TPS65941120 GPIO8 is configured as an input to disable the watchdog. Typically, during development this
pin is tied high, so that when the nRSTOUT bit is set WD_PWRHOLD is also set. The configuration of this pin
can be utilized for other features or functions but this requires servicing the watchdog before it expires. The
watchdog long window is 772 seconds, Table 5-13.
Write 0x12:0x09:0x00:0xBF // Disable Watchdog
Write 0x48:0x38:0x01:0x00 // configure GPIO8 as a pushpull output
When it is time to enable and configure the watchdog, then in addition to enabling the watchdog the
WD_PWR_HOLD must be cleared.
Write 0x12:0x09:0x00:0xFB // Clear WD_PWRHOLD
Write 0x12:0x09:0x40:0xBF // Enable Watchdog
In addition to the GPIO8 of the TPS65941120 there are also the feedback pins for BUCK4 on the TPS65941120.
This monitor can be used independently since the BUCK4 regulator is multiphased with BUCKs 1, 2 and 3.
When enabling a monitor, the built in self-test is performed. Please refer to the data sheet for an explanation of
the monitor self-test. If the self-test fails this results in a Moderate error that triggers the TO_SAFE_ORDERLY
power sequence.
Unlike the GPIO, the BUCK monitor can become part of the PFSM by assigning a group to the BUCK regulator
and unmasking the OV/UV interrupts. Per Table 5-7, the BUCK4_GRP_SEL is not assigned a group.
Table 7-3. Rail Group Associations
Selected Rail group Selection PFSM Trigger Description
No Group Assigned None OV/UV can set nINT pin for MCU
interrogation.
MCU Rail Group MCU Power Error OV/UV can trigger TO_SAFE
Soc Rail Group SoC Power Error OV/UV can trigger
Other Rail Group Orderly Shutdown OV/UV can triggerTO_SAFE_ORDERLY
In this example BUCK4 is used to monitor a 0.8V supply. The wait statement ensures that the built in self-test
of the monitors is completed before the OV and UV monitors are unmasked. Refer to the TPS6594-Q1Power
Application Examples www.ti.com
52 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
SLVUCJ9 – FEBRUARY 2023
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