Management IC (PMIC) with 5 Bucks and 4 LDOs for Safety- Relevant Automotive Applications data sheet for
more details.
Write 0x48:0x14:0x37:0x00 // Set to 0.8V
Write 0x48:0x0B:0x07:0xF1 // Set slew rate to 0.31mV/us
Write 0x48:0x41:0xA0:0x0F // SOC rail group
Write 0x48:0x4A:0x30:0xCF // Mask OV/UV
Write 0x48:0x0A:0x10:0xEF // Enable BUCK4 Monitor
// Startup = 220us, ramp = 42us, settling = 105us, OV/UV test=50us
wait 500us
Write 0x48:0x4A:0x00:0xCF // Unmask OV/UV
With the TO_SAFE and TO_SAFE_ORDERLY sequences the PMICs transition through the SAFE RECOVERY
state as well as hardware states INIT and BOOT BIST. Through this transition the user registers are restored
with the NVM settings. For both the GPIO and BUCK monitor customizations, these customizations are not
preserved and must be re-applied with every power cycle and transition through the hardware states.
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SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
53
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