6.3 Power Sequences
6.3.1 TO_SAFE_SEVERE and TO_SAFE
The TO_SAFE_SEVERE and TO_SAFE are distinct sequences that occur before transitioning to the SAFE
state. Both sequences shut down all rails without delay and force EN_DRV low. The TO_SAFE_SEVERE
sequence immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LDOs.
The pulldown is enabled to prevent any damage of the PMICs in case of over voltage on VCCA or thermal
shutdown. The timing is illustrated in Figure 6-2. The TO_SAFE sequence does not reset the BUCK regulators
until after the regulators are turned off.
Resource PMIC Delay Diagram Total Delay Rail Name
GPIO11
TPS65941120-Q1
(Leo A)
0 us EN_MCU3V3_VIO
BUCK1234
TPS65941120-Q1
(Leo A)
0 us VDD_DDR_1V1
LDO1
TPS65941120-Q1
(Leo A)
0 us VDD_DDR_1V1
BUCK5
TPS65941120-Q1
(Leo A)
0 us VDD_DDR_1V1
LDO3
TPS65941120-Q1
(Leo A)
0 us VDD_DDR_1V1
LDO4
TPS65941120-Q1
(Leo A)
0 us VDD_DDR_1V1
LDO2
TPS65941120-Q1
(Leo A)
0 us VDD_DDR_1V1
nRSTOUT_SOC
TPS65941120-Q1
(Leo A)
0 us EN_MCU3V3_VIO
GPIO9
TPS65941120-Q1
(Leo A)
0 us EN_MCU3V3_VIO
BUCK2
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
BUCK4
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
BUCK5
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
LDO3
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
LDO1
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
LDO4
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
BUCK1
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
BUCK3
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
LDO2
TPS65941421-Q1
(Leo B)
0 us VDD_DDR_1V1
GPIO11
TPS65941421-Q1
(Leo B)
0 us EN_MCU3V3_VIO
GPIO3
TPS65941421-Q1
(Leo B)
0 us EN_MCU3V3_VIO
BUCK1234
LP876411B5-Q1
(Hera C)
0 us VDD_DDR_1V1
Figure 6-2. TO_SAFE_SEVERE and TO_SAFE Power Sequences
Pre-Configurable Finite State Machine (PFSM) Settings www.ti.com
36 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
SLVUCJ9 – FEBRUARY 2023
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