Table 6-1. State Transition Triggers (continued)
Trigger Priority (ID)
Immediate
(IMM)
REENTERANT PFSM Current State
PFSM
Destination
State
Power Sequence or
Function Executed
I2C_2 bit is
high
(3)
13 False True ACTIVE, MCU ONLY No State
Change
Enable I
2
C CRC on
I
2
C1 and I
2
C2 on all
devices.
(4)
ON Request 14 False False
STANDBY, ACTIVE,
MCU ONLY, Suspend-
to-RAM
ACTIVE
TO_ACTIVE
WKUP1 goes
high
15 False False
STANDBY, ACTIVE,
MCU ONLY, Suspend-
to-RAM
ACTIVE
NSLEEP1 and
NSLEEP2 are
high
(5)
16 False False
STANDBY, ACTIVE,
MCU ONLY, Suspend-
to-RAM
ACTIVE
MCU On Request 17 False False STANDBY, ACTIVE
(7)
,
MCU ONLY, Suspend-
to-RAM
MCU ONLY TO_MCU
WKUP2 goes
high
18 False False STANDBY, ACTIVE
(7)
,
MCU ONLY, Suspend-
to-RAM
MCU ONLY
NSLEEP1 goes
low and
NSLEEP2 goes
high
(5)
19 False False
ACTIVE, MCU ONLY,
Suspend-to-RAM
MCU ONLY
NSLEEP1 goes
low and
NSLEEP2 goes
low
(5)
20 False False ACTIVE, MCU ONLY
Suspend-to-
RAM
TO_RETENTION
NSLEEP1 goes
high and
NSLEEP2 goes
low
(5)
21 False False ACTIVE, MCU ONLY Suspend-to-
RAM
I2C_0 bit goes
high
(3)
22
(9)
False False
STANDBY, ACTIVE,
MCU ONLY
STANDBY
(2)
TO_STANDBY
I2C_3 bit goes
high
(3)
23
(9)
False False ACTIVE, MCU ONLY No State
Change
Devices are prepared
for OTA NVM update.
(6)
(1) From the SAFE state, the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY. From
the SAFE_RECOVERY state, the recovery counter is incremented and compared to the recovery count threshold (see
RECOV_CNT_REG_2, in Table 5-10). If the recovery count threshold is reached, then the PMICs halt recovery attempts and require a
power cycle. Refer to the data sheet for more details.
(2) If the LP_STANDBY_SEL bit is set in the TPS65941120-Q1 (see RTC_CTRL_2, in Table 5-10), then the PFSM transitions to the
hardware FSM state of LP_STANDBY. When LP_STANDBY is entered, then please use the appropriate mechanism to wakeup the
device as determined by the means of entering LP_STANDBY. Refer to the
data sheet for more details. LP_STANDBY_SEL in the
TPS65941421-Q1 and LP876411B5-Q1 are not applicable to the PFSM triggers.
(3) I2C_0, I2C_1, I2C_2 and I2C_3 are self-clearing triggers.
(4) Enabling the I
2
C CRC, enables the CRC on both I2C1 and I2C2, however, the I2C2 is disabled for 2ms after the CRC is enabled. Be
aware when using the watchdog Q&A before enabling I
2
C CRC. The recommendation is to enable the I
2
C CRC first, and then after
2ms, start the watchdog Q&A.
(5) NSLEEP1 and NSLEEP2 of the primary PMIC can be accessed through the GPIO pin or through a register bit. If either the register bit
or the GPIO pin is pulled high, the NSLEEPx value is read as a high logic level.
(6) After completion of an OTA update, the processor is required to initiate a reset of the PMICs to apply the new NVM settings.
(7) When in the ACTIVE mode, the ON Request to MCU ONLY trigger cannot be accessed while other higher priority triggers, like
NSLEEP1=NSLEEP2=HIGH, are still active.
(8) These triggers can originate from either the TPS65941120-Q1, TPS65941421-Q1, and LP876411B5-Q1.
(9) Trigger IDs 22 and 23 are not available until the NSLEEP bits are masked: NSLEEP2_MASK=NSLEEP1_MASK=1.
(10) Trigger IDs 0, 4, and 24 (not shown) are enabled and activated by the power sequences. These triggers are used to manage the
transition between the PFSM and the FSM.
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
35
Copyright © 2023 Texas Instruments Incorporated
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