Note
TO_SAFE_SEVERE and TO_SAFE Power Sequences
After the power sequence shown in Figure 6-2, the TO_SAFE sequence executes the following instructions:
//TPS65941120 and TPS65941421
// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
// Reset all BUCK regulators
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x1F MASK=0xE0
//PL876411B5
//Reset all BUCK regulators
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x0F MASK=0xF0
The resetting of the BUCK regulators is done in preparation to transitioning to the SAFE_RECOVERY state.
SAFE_RECOVERY means that the PMIC leaves the mission state. The SAFE_RECOVERY state is where the
recovery mechanism increments the recovery counter and determines if the recovery count threshold (see Table
5-10) is reached before attempting to recover.
The TO_SAFE_SEVERE sequence executes the following instruction after the power sequence:
// TPS65941120 and TPS65941421
// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
The TPS65941120 has an additional delay of 500 ms at the end of the TO_SAFE_SEVERE sequence. It is
important to note that the recovery is not attempted until after the sequence delay is complete.
6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs
using the recommended power down sequence and proceed to the SAFE state.
If an OFF request occurs, such as the ENABLE pin of the primary TPS6594-Q1 device being pulled low,
the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or
LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the SAFE state. The power sequence for
both of these events is shown in Figure 6-3.
Both the TO_SAFE_ORDERLY and TO_STANDBY sequences set the SPMI_LP_EN and
FORCE_EN_DRV_LOW in the TPS65941120 while only the SPMI_LP_EN is set in the TPS65941421 and
LP876411B5.
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
37
Copyright © 2023 Texas Instruments Incorporated
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