Texas Instruments TPS65941120-Q1

Resource PMIC Delay Diagram Total Delay Rail Name
GPIO9
TPS65941120-Q1
(Leo A)
3500 us EN_MCU3V3_VIO
LDO2
TPS65941120-Q1
(Leo A)
3500 us
VDD_MCU_
GPIORET_3V3
LDO2
TPS65941421-Q1
(Leo B)
3500 us VDD_GPIORET_3V3
GPIO3
TPS65941421-Q1
(Leo B)
3000 us EN_DDR_VDD1
LDO4
TPS65941120-Q1
(Leo A)
3000 us VDA_MCU_1V8
LDO3
TPS65941120-Q1
(Leo A)
3000 us VDD_MCUIO_1V8
BUCK5
TPS65941120-Q1
(Leo A)
2500 us VDD_MCU_0V85
LDO1
TPS65941120-Q1
(Leo A)
2500 us VDD_MCU_WK_0V8
LDO1
TPS65941421-Q1
(Leo B)
2500 us VDD_WK_0V8
BUCK4
TPS65941421-Q1
(Leo B)
500 us VDD_DDR_1V1
nRSTOUT
TPS65941120-Q1
(Leo A)
0 us H_MCU_PORz
GPIO11
(nRSTOUT_SOC)
TPS65941120-Q1
(Leo A)
0 us H_SOC_PORz
BUCK5
TPS65941421-Q1
(Leo B)
500 us VDD_RAM_0V85
LDO3
TPS65941421-Q1
(Leo B)
2500 us VDA_DLL_0V8
BUCK1234
LP876411B5-Q1
(Hera C)
2500 us VDD_CORE_0V8
BUCK1234
TPS65941120-Q1
(Leo A)
2500 us VDD_CPU_AVS
LDO4
TPS65941421-Q1
(Leo B)
3000 us VDD_PLL_1V8
BUCK1
TPS65941421-Q1
(Leo B)
3000 us VDD_IO_1V8
BUCK3
TPS65941421-Q1
(Leo B)
3000 us VDD_PHY_1V8
GPIO11
TPS65941421-Q1
(Leo B)
3500 us EN_3V3_VIO
Figure 6-3. TO_SAFE_ORDERLY and TO_STANDBY Power Sequence
At the end of the TO_SAFE_ORDERLY the PMICs executes a delay based on the value stored in register R2,
which is runtime configurable and has a default value of approximately 16 ms, before executing the following
instructions:
/TPS65941120 and TPS65941421
// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
// Reset all BUCK regulators
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x1F MASK=0xE0
//LP876411B5
//Reset all BUCK regulators
REG_WRITE_MASK_IMM ADDR=0x87 DATA=0x0F MASK=0xF0
Pre-Configurable Finite State Machine (PFSM) Settings www.ti.com
38 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
SLVUCJ9 – FEBRUARY 2023
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