The resetting of the BUCK regulators is done in preparation to transitioning to the SAFE_RECOVERY state.
SAFE_RECOVERY means that the PMIC leaves the mission state. The SAFE_RECOVERY state is where the
recovery mechanism increments the recovery counter and determines if the recovery count threshold (see Table
5-10) is reached before attempting to recover.
At the end of the TO_STANDBY sequence, the 16 ms delay is found in the TPS65941120 device only and
the same AMUXOUT_EN, CLKMON_EN, and LPM_EN bit manipulations are made in all PMICs. The BUCKs
are not reset. After these instructions, the TPS65941120 performs an additional check to determine if the
LP_STANDBY_SEL (see Table 5-10) is true. If true then the PMICs enter the LP_STANDBY state and leave
the mission state. If the LP_STANDBY_SEL is false, then the PMICs remain in the mission state defined by
STANDBY in Configured States.
6.3.3 ACTIVE_TO_WARM
The ACTIVE_TO_WARM sequence can be triggered by either a watchdog or ESM_MCU error. In the event
of a trigger, the nRSTOUT and nRSTOUT_SOC signals are driven low and the recovery count (register
RECOV_CNT_REG_1) increments. Then, all BUCKs and LDOs are reset to their default voltages. The PMICs
remain in the ACTIVE state.
Note
GPIOs do not reset during the sequence as shown in Figure 6-4
At the beginning of the sequence the following instructions are executed:
//TPS65941120
// Set FORCE_EN_DRV_LOW
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x08 MASK=0xF7
// Clear nRSTOUT and nRSTOUT_SOC
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x00 MASK=0xFC
// Increment the recovery counter
REG_WRITE_MASK_IMM ADDR=0xa5 DATA=0x01 MASK=0xFE
Note
The watchdog or ESM error is an indication of a significant error that has taken place outside
of the PMIC. The PMIC does not actually transition through the safe recovery as with an
MCU_POWER_ERR, however, in order to maintain consistency all of the regulators are returned
to the values stored in NVM and the recovery counter is incremented. If the recovery counter exceeds
the recovery count threshold the resulting RECOV_CNT_INT sends the PMICs to the safe recovery
state.
Note
After the ACTIVE_TO_WARM sequence the processor is responsible for managing the EN_DRV and
recovery counter. At the end of the sequence the 'FORCE_EN_DRV_LOW' bit is cleared so that the
MCU can set the ENABLE_DRV bit.
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
39
Copyright © 2023 Texas Instruments Incorporated
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