Note
After the TO_ACTIVE sequence the MCU is responsible for managing the EN_DRV.
6.3.9 TO_RETENTION
The C and D triggers, defined by the NSLEEPx bits or pins, trigger the TO_RETENTION sequence. This
sequence disables all power rails and GPIOs that are not supplying the retention rails, as described in
Figure 3-1. The sequence can be modified using the I2C_5, I2C_6, and I2C_7 bits found in register
FSM_I2C_TRIGGERS. These bits need to be set by I
2
C in both PMICs before a trigger for the retention state
occurs. If the I2C_5, I2C_6, and I2C_7 bits are set high in all PMICs, they enter the DDR and GPIO retention
state as shown in Figure 6-13. If I2C_5, I2C_6, and I2C_7 are set low, these components associated with DDR
and GPIO retention do not remain active, as shown in Figure 6-12.
Note
The I2C_x bits need to be set or cleared by I
2
C in both PMICs before a trigger to the retention state
occurs. The I2C_x triggers are not self-clearing and must be maintained during operation.
The following PMIC PFSM instructions are executed automatically in the beginning of the power sequence to
configure the PMICs:
// TPS65941120
// Set LPM_EN, Clear NRSTOUT_SOC and NRSTOUT
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xF8
// Set SPMI_LP_EN and FORCE_EN_DRV_LOW
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x18 MASK=0xE7
// TPS65941421 LP876411B5
// Set SPMI_LP_EN
REG_WRITE_MASK_IMM ADDR=0x82 DATA=0x10 MASK=0xEF
www.ti.com Pre-Configurable Finite State Machine (PFSM) Settings
SLVUCJ9 – FEBRUARY 2023
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TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
47
Copyright © 2023 Texas Instruments Incorporated
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