Texas Instruments TPS65941120-Q1 User Manual

6.3.8 TO_ACTIVE
When a trigger causes the TO_ACTIVE sequence to execute, all rails power up in the recommended power up
sequence as shown in .
At the beginning of the TO_ACTIVE sequence both PMICs clear SPMI_LP_EN and LPM_EN and set
AMUXOUT_EN and CLKMON_EN.
Resource PMIC Delay Diagram Total Delay Rail Name
GPIO9
TPS65941120-Q1
(Leo A)
0 us EN_MCU3V3_VIO
GPIO11
TPS65941421-Q1
(Leo B)
0 us EN_3V3_IO
LDO2
TPS65941120-Q1
(Leo A)
0 us
VDD_MCU_
GPIORET_3V3
LDO2
TPS65941421-Q1
(Leo B)
0 us VDD_GPIORET_3V3
GPIO3
TPS65941421-Q1
(Leo B)
1700 us EN_DDR_VDD1
LDO4
TPS65941120-Q1
(Leo A)
1700 us VDA_MCU_1V8
LDO3
TPS65941120-Q1
(Leo A)
1700 us VDD_MCUIO_1V8
BUCK3
TPS65941421-Q1
(Leo B)
1700 us VDD_PHY_1V8
BUCK1
TPS65941421-Q1
(Leo B)
1700 us VDD_IO_1V8
LDO4
TPS65941421-Q1
(Leo B)
1700 us VDD_PLL_1V8
BUCK5
TPS65941120-Q1
(Leo A)
2700 us VDD_MCU_0V85
LDO1
TPS65941120-Q1
(Leo A)
2700 us VDD_MCU_WK_0V8
BUCK1234
TPS65941120-Q1
(Leo A)
2700 us VDD_CPU_AVS
BUCK1234
LP876411B5-Q1
(Hera C)
2700 us VDD_CORE_0V8
LDO1
TPS65941421-Q1
(Leo B)
2700 us VDD_WK_0V8
LDO3
TPS65941421-Q1
(Leo B)
2700 us VDA_DLL_0V8
BUCK5
TPS65941421-Q1
(Leo B)
4700 us VDD_RAM_0V85
BUCK4
TPS65941421-Q1
(Leo B)
4700 us VDD_DDR_1V1
nRSTOUT
TPS65941120-Q1
(Leo A)
12700 us H_MCU_PORz
GPIO11
TPS65941120-Q1
(Leo A)
12700 us H_SOC_PORz
Figure 6-11. TO_ACTIVE Sequence
At the end of the TO_ACTIVE sequence the 'FORCE_EN_DRV_LOW' bit is cleared.
Pre-Configurable Finite State Machine (PFSM) Settings www.ti.com
46 TPS65941120-Q1, TPS65941421-Q1 and LP876411B5-Q1 PMIC User Guide
for J721S2, PDN-0A
SLVUCJ9 – FEBRUARY 2023
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Texas Instruments TPS65941120-Q1 Specifications

General

Brand	Texas Instruments
Model	TPS65941120-Q1
Category	Microcontrollers
Language	English