2 Troubleshooting Procedures 2.4 System Board Troubleshooting
2-22 TECRA M3 Maintenance Manual (960-507)
Table 2-5 Debug port LED boot mode status (3/7)
LED Status Item Contents/Message
01h Check of DRAM type and size (Reading DRAM size at Warm Boot)
(DRAM check at Cold Boot))
Check of DRAM size (HLT when the DRAM type is 0.) 11h
SM-RAM stack area test (HLT when the stack area can not be used.)
Permission of Cache (L1 cache
only)
CMOS access test (at Cold Boot) (HLT when an error is detected.)
Battery level check of CMOS
CMOS checksum check
Initialization of CMOS data (1)
Setting of IRT status (Boot status, the remaining bit is 0.)
02h
Storing DRAM size in CMOS
Not resume when a CMOS error occurred Resume branch (at Cold Boot)
Not resume when resume status code is not set
SM-RAM checksum check (Resume error 0F4H)
Check of memory configuration change
RAM area checksum check in system BIOS (Resume
error 0FAH)
PnP RAM checksum check (Resume error 0F8H)
Resume error check
PIT test and initialization (HLT when refresh signal is not
changed.)
Initialization of PIT CH0 (Setting of timer interrupt
interval to 55ms)
Initialization of PIT CH2 (Setting of sound generator
frequency to 664Hz)
Transition to RESUME-MAIN
Reset of CPU clock to low
Prohibition of all SMI
Clearance of resume status
Return to ROM
Resume error process
Initialization of memory map
Check hibernation from S4 OS
Check hibernation status code
03h
Boot mode process (in no resume)
ROM/RAM copy of system BIOS (HLT when copied
BIOS checksum error.)
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