KC705 Evaluation Board 3
UG810 (v1.8) March 20, 2018 www.xilinx.com
05/10/2013 1.3 Updated Figure 1-1 to show v 1.1 board. Updated Table 1-1, page 10: callout 1 to
identify Fansink, callouts 25and 26 pointing to User I/O. Added Table 1-9 Clock
Source to FPGA U1 Connections. Updated Programmable User Clock Source,
page 29 to include I2C address. Updated Table 1-17, page 43 for naming pins 18
and 19. Added Note to Table 1-14, page 42. Updated I2C Bus Switch, page 52 to
show TI device instead of NXP Semiconductor, deleted; updated [Ref 19]. Added
Figure 1-28, page 57 Rotary Switch, and Figure 1-29, page 58 GPIO SMAs J13 and
J14. Added Note to Appendix C, Master Constraints File Listing. Updated
Appendix D, Board Setup, step 1 of installation procedure. Updated Appendix F,
Additional Resources to include CE PC Test reference.
12/10/2012 1.2 Replaced direct, inline links to external references in the body text with indirect
references to the links in a numbered list in Appendix G, Additional Resources and
Legal Notices. Revised the value for frequency jitter for the System Clock Source,
page 29. Reset conditions are added to Jitter Attenuated Clock, page 32 Revised
jumper information for SFP_RS1, page 42 in Table 1-15. Revised contents and
organization of Appendix F, Additional Resources.
04/05/2012 1.1 Updated links from Table 1-1, page 10. Revised the JTAG configuration mode USB
cable description under FPGA Configuration, page 12. Added Encryption Key
Backup Circuit, page 13 and Table 1-4, page 15. Added links to User SMA Clock
Input in Table 1-8, page 28. Added link to Si570 device vendor on page 30. Added
Ethernet PHY Status LEDs, page 54 and Figure 1-24, page 54. Updated Power
On/Off Slide Switch SW15, page 60 and added Figure 1-32, page 61. Revised FPGA
Mezzanine Card Interface, page 63 and Table 1-28, page 64 and Table 1-29,
page 69. Added description of power module cooling requirement to Power
Management, page 71. Added Cooling Fan Control, page 74. Updated Table 1-35,
page 80. Added references to Documents, page 85. Added Appendix E, Compliance
with European Union Directives and Standards, Appendix D, Board Setup, and
Appendix E, Board Specifications.
01/23/2012 1.0 Initial Xilinx release.
Date Version Revision
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