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Xilinx ML505 - Page 12

Xilinx ML505
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12 www.xilinx.com ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Chapter 1: ML505/ML506/ML507 Evaluation Platform
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• RS-232 serial port, DB9 and header for second serial port
• 16-character x 2-line LCD display
• One 8-Kb IIC EEPROM and other IIC capable devices
• PS/2 mouse and keyboard connectors
• Video input/output
♦ Video input (VGA)
♦ Video output DVI connector (VGA supported with included adapter)
• ZBT synchronous SRAM, 9 Mb on 32-bit data bus with four parity bits
• Intel P30 StrataFlash linear flash chip (32 MB)
• Serial Peripheral Interface (SPI) flash (2 MB)
• 10/100/1000 tri-speed Ethernet PHY transceiver and RJ-45 with support for MII,
GMII, RGMII, and SGMII Ethernet PHY interfaces
• USB interface chip with host and peripheral ports
• Rechargeable lithium battery to hold FPGA encryption keys
• JTAG configuration port for use with Parallel Cable III, Parallel Cable IV, or Platform
USB download cable
• Onboard power supplies for all necessary voltages
• Temperature and voltage monitoring chip with fan controller
• 5V @ 6A AC adapter
• Power indicator LED
• MII, GMII, RGMII, and SGMII Ethernet PHY Interfaces
• GTP/GTX: SFP (1000Base-X)
• GTP/GTX: SMA (RX and TX Differential Pairs)
• GTP/GTX: SGMII
• GTP/GTX: PCI Express® (PCIe™) edge connector (x1 Endpoint)
• GTP/GTX: SATA (dual host connections) with loopback cable
• GTP/GTX: Clock synthesis ICs
• Mictor trace port
• BDM debug port
• Soft touch port
• System monitor
Downloaded from Elcodis.com electronic components distributor

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