Xilinx ML505 User Manual

ML505/ML506/ML507 Evaluation Platform www.xilinx.com 31
UG347 (v3.1.1) October 7, 2009
Detailed Description
R
21. 10/100/1000 Tri-Speed Ethernet PHY
The board contains a Marvell Alaska PHY device (88E1111) operating at
10/100/1000 Mb/s. The board supports MII, GMII, RGMII, and SGMII interface modes
with the FPGA. The PHY is connected to a Halo HFJ11-1G01E RJ-45 connector with built-in
magnetics. The PHY is configured to default at power-on or reset to the settings shown in
Table 1-15. These settings can be overwritten via software. All modes are selectable by the
jumpers as shown in Table 1-15.
Table 1-15: Board Connections for PHY Configuration Pins
Config Pin
Connection on
Board
Bit[2]
Definition and Value
Bit[1]
Definition and Value
Bit[0]
Definition and Value
CONFIG0 V
CC
2.5V PHYADR[2] = 1 PHYADR[1] = 1 PHYADR[0] = 1
CONFIG1 Ground ENA_PAUSE = 0 PHYADR[4] = 0 PHYADR[3] = 0
CONFIG2 V
CC
2.5V ANEG[3] = 1 ANEG[2] = 1 ANEG[1] = 1
CONFIG3 V
CC
2.5V ANEG[0] = 1 ENA_XC = 1 DIS_125 = 1
CONFIG4
V
CC
2.5V or
LED_DUPLEX or
LED_LINK1000
(Set by J23 and J24)
HWCFG_MODE[2] = 0 or
1 (Set by J23 and J24)
HWCFG_MODE[1] = 1 HWCFG_MODE[0] = 1
CONFIG5 V
CC
2.5V or
LED_LINK10
(Set by J22)
DIS_FC = 1 DIS_SLEEP = 1 HWCFG_MODE[3] = 1
CONFIG6 LED_RX SEL_BDT = 0 INT_POL = 1 75/50Ω = 0
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Xilinx ML505 Specifications

General

Brand	Xilinx
Model	ML505
Category	Motherboard
Language	English