Xilinx RocketIO User Manual

132 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Appendix A: RocketIO Transceiver Timing Model
R
T
GCCK
_TRST/T
GCKC
_TRST Control inputs TXRESET
T
GCCK
_TKCH/T
GCKC
_TKCH Control inputs TXCHARISK[3:0]
T
GCCK
_TCDM/T
GCKC
_TCDM Control inputs TXCHARDISPMODE[3:0]
T
GCCK
_TCDV/T
GCKC
_TCDV Control inputs TXCHARDISPVAL[3:0]
T
GDCK
_CFGIN/T
GCKD
_CFGIN Data inputs CONFIGIN
T
GDCK
_TDAT/T
GCKD
_TDAT Data inputs TXDATA[31:0]
Clock to Out:
T
GCKST
_TBERR Status outputs TXBUFERR
T
GCKST
_TKERR Status outputs TXKERR[3:0]
T
GCKDO
_TRDIS Data outputs TXRUNDISP[3:0]
T
GCKDO
_CFGOUT Data outputs CONFIGOUT
Clock:
T
TX2PWH
Clock pulse width, High state TXUSRCLK2
T
TX2PWH
Clock pulse width, Low state TXUSRCLK2
Table A-4: Parameters Relative to the TX User Clock2 (TXUSRCLK2) (Continued)
Parameter Function Signals
Table A-5: Miscellaneous Clock Parameters
Parameter Function Signals
Clock:
T
REFPWH
Clock pulse width, High state REFCLK
(1)
T
REFPWL
Clock pulse width, Low state REFCLK
(1)
T
BREFPWH
Clock pulse width, High state BREFCLK
(2)
T
BREFPWL
Clock pulse width, Low state BREFCLK
(2)
T
TX2PWH
Clock pulse width, High state TXUSRCLK
(3)
T
TX2PWL
Clock pulse width, Low state TXUSRCLK
(3)
Notes:
1. REFCLK is not synchronous to any RocketIO signals.
2. BREFCLK is not synchronous to any RocketIO signals.
3. TXUSRCLK is not synchronous to any RocketIO signals.
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English