154 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
R
2-byte clock 43
32-bit alignment design 98
4-byte clock 47
High-Speed Serial Trace Design 115
HSPICE 121
I
Implementation Tools 121
J
Jitter
and BREFCLK
41
and use of DCM with REFCLK 39
deterministic and random, defined
107
parameters 107, 108
PCB trace length mismatch 115
K
K-Characters, valid (table) 143
L
Latency, Data Path 57
M
Miscellaneous Signals 90
Modifiable Primitives (table) 34
Multiplexed Clocking Scheme
with DCM
55
without DCM 55
P
Package Pins 123
Par 121
Passive Filtering 111
PCB Design Requirements 109
Ports & Attributes (by function)
8B/10B encoding/decoding
61
buffers, fabric interface 90
channel bonding 81
clock correction 73
CRC 85
SERDES alignment 67
synchronization logic 76
Ports (defined)
CHBONDDONE
83
CHBONDI 83
CHBONDO 83
ENCHANSYNC 81
ENMCOMMAALIGN 68
ENPCOMMAALIGN 68
LOOPBACK 91
POWERDOWN 120
RXBUFSTATUS 90
RXCHARISCOMMA 71
RXCHARISK 63
RXCHECKINGCRC 88
RXCLKCORCNT 76, 83
RXCOMMADET 71
RXCRCERR 88
RXDISPERR 64
RXLOSSOFSYNC 77, 83
RXNOTINTABLE 64
RXPOLARITY 91
RXREALIGN 70
RXRECCLK 56
RXRUNDISP 63
TXBUFERR 90
TXBYPASS8B10B 61
TXCHARDISPMODE 62
TXCHARDISPVAL 62
TXCHARISK 63
TXFORCECRCERR 89
TXINHIBIT 91
TXKERR 63
TXPOLARITY 91
TXRUNDISP 63
Ports (table) 24
Power Supply
passive filtering
111
power conditioning 109
Power Supply Circuit Using Approved
Regulator (figure)
110
Pre-emphasis
available values
104
overview 104
scope screen captures 105, 106
Q
Qualified Linear Regulators (table) 110
R
Random Jitter (RJ) 108
Receive Data Path 32-bit Alignment 93
Receiver Buffer 89
Reference Clock
generating
119
oscillator (Epson), for LVPECL 119
oscillator (Pletronics), for LVDS 119
Reset/Power Down 57
RocketIO transceiver
additional resources
18
analog design considerations 103
application notes 145
attributes (table) 29
basic architecture and capabilities 21
block diagram 22, 128
channel bonding (channel align-
ment)
79
characterization reports 149
clocking 39
communications standards support-
ed
21
CRC (Cyclic Redundancy Check) 84
default attribute values (tables) 34
design notes
analog
120
digital 93
digital design considerations 39
modifiable primitives 34
number of MGTs per device type 21
PCB design requirements 109
ports (table) 24
powering 120
related online documents 145
reset/power down 57
simulation and implementation 121
unused transceivers 120
valid control characters (K-charac-
ters)
143
valid data characters 135
white papers 151
Routing Serial Traces 115
S
SERDES Alignment
overview
67
ports and attributes 67
Serial I/O Description 103
Serializer 67
Setup/Hold Times of Inputs Relative to
Clock
129
Simulation Models 121
SmartModels 121
Synchronization Logic
overview
76
ports and attributes 76
Product Not Recommended for New Designs
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