Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 47
UG024 (v3.0) February 22, 2007
Clocking
R
any interface logic. Both USRCLK and USRCLK2 are aligned on the falling edge, since
USRCLK_M is 180° out of phase when using local inverters with the transceiver.
Note:
These local MGT clock input inverters, shown and noted in Figure 2-4, are not included
in the FOUR_BYTE_CLK templates.
VHDL Template
-- Module: FOUR_BYTE_CLK
-- Description: VHDL submodule
-- DCM for 4-byte GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity FOUR_BYTE_CLK is
port (
REFCLKIN : in std_logic;
RST : in std_logic;
USRCLK_M : out std_logic;
USRCLK2_M : out std_logic;
REFCLK : out std_logic;
LOCK : out std_logic
);
end FOUR_BYTE_CLK;
--
architecture FOUR_BYTE_CLK_arch of FOUR_BYTE_CLK is
--
-- Components Declarations:
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
--
component IBUFG
port (
Figure 2-4: Four-Byte Clock
CLKDV
CLKDV_DIVIDE = 2
MGT clock input invert-
ers (acceptable skew)
MGT + DCM for 4-Byte Data Path
GT_std_4
REFCLKSEL
REFCLK
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLKIN
CLKFB
RST
DCM
CLK0
0
BUFG
BUFG
Clocks for 4-Byte Data Path
TXUSRCLK
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
REFCLK
UG024_03_112202
REFCLK_P
IBUFGDS
REFCLK_N
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English