Xilinx RocketIO - Page 48

48 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 2: Digital Design Considerations
R
I : in std_logic;
O : out std_logic
);
end component;
--
component DCM
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
DSSEN : in std_logic;
PSINCDEC : in std_logic;
PSEN : in std_logic;
PSCLK : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector ( 7 downto 0 )
);
end component;
--
-- Signal Declarations:
--
signal GND : std_logic;
signal CLK0_W : std_logic;
signal CLKDV_W : std_logic;
signal USRCLK2_M_W: std_logic;
begin
USRCLK2_M <= USRCLK2_M_W;
GND <= '0';
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN => REFCLK,
CLKFB => USRCLK_M,
DSSEN => GND,
PSINCDEC => GND,
PSEN => GND,
PSCLK => GND,
RST => RST,
CLK0 => CLK0_W,
CLKDV => CLKDV_W,
LOCKED => LOCK
);
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
Product Not Recommended for New Designs