Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 27
UG024 (v3.0) February 22, 2007
List of Available Ports
R
TXCHARDISPMODE
(3)
I 1, 2, 4 If 8B/10B encoding is enabled, this bus determines what mode of
disparity is to be sent. When 8B/10B is bypassed, this becomes the first
bit transmitted (Bit “a”) of the 10-bit encoded TXDATA bus section (see
Figure 2-13, page 65) for each byte specified by the byte-mapping.
TXCHARDISPVAL
(3)
I 1,2,4 If 8B/10B encoding is enabled, this bus determines what type of
disparity is to be sent. When 8B/10B is bypassed, this becomes the
second bit transmitted (Bit “b”) of the 10-bit encoded TXDATA bus
section (see Figure 2-13, page 65) for each byte specified by the byte-
mapping section.
TXCHARISK
(3)
I 1, 2, 4 If 8B/10B encoding is enabled, this control bus determines if the
transmitted data is a K-character or a Data character. A logic High
indicates a K-character.
TXDATA
(3)
I 8, 16, 32 Transmit data that can be 1, 2, or 4 bytes wide, depending on the
primitive used. TXDATA [7:0] is always the last byte transmitted. The
position of the first byte depends on selected TX data path width.
TXFORCECRCERR I 1 Specifies whether to insert error in computed CRC.
When TXFORCECRCERR = TRUE, the transmitter corrupts the
correctly computed CRC value by XORing with the bits specified in
attribute TX_CRC_FORCE_VALUE. This input can be used to test
detection of CRC errors at the receiver.
TXINHIBIT I 1 If a logic High, the TX differential pairs are forced to be a constant 1/0.
TXN = 1, TXP = 0
TXKERR
(3)
O 1,2,4 If 8B/10B encoding is enabled, this signal indicates (High) when the
K-character to be transmitted is not a valid K-character. Bits correspond
to the byte-mapping scheme.
TXN
(4)
O 1 Transmit differential port (FPGA external)
TXP
(4)
O 1 Transmit differential port (FPGA external)
TXPOLARITY I 1 Specifies whether or not to invert the final transmitter output. Able to
reverse the polarity on the TXN and TXP lines. Deasserted sets regular
polarity. Asserted reverses polarity.
TXRESET I 1 Synchronous TX system reset that “recenters” the transmit elastic
buffer. It also resets 8B/10B encoder and other internal transmission
registers. It does not reset the transmission PLL.
TXRUNDISP
(3)
O 1, 2, 4 Signals the running disparity after this byte is encoded. Low indicates
negative disparity, High indicates positive disparity.
TXUSRCLK I 1 Clock output from a DCM or a BUFG that is clocked with a reference
clock. This clock is used for writing the TX buffer and is frequency-
locked to the reference clock.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port I/O
Port
Size
Definition
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English