Xilinx RocketIO User Manual

26 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 1: RocketIO Transceiver Overview
R
RXLOSSOFSYNC O 2 Status related to byte-stream synchronization
(RX_LOSS_OF_SYNC_FSM)
If RX_LOSS_OF_SYNC_FSM = TRUE, RXLOSSOFSYNC indicates the
state of the FSM:
Bit 1 = Loss of sync (High)
Bit 0 = Resync state (High)
If RX_LOSS_OF_SYNC_FSM = FALSE, RXLOSSOFSYNC indicates:
Bit 1 = Received data invalid (High)
Bit 0 = Channel bonding sequence recognized (High)
RXN
(4)
I 1 Serial differential port (FPGA external)
RXNOTINTABLE
(3)
O 1,2,4 Status of encoded data when the data is not a valid character when
asserted High. Applies to the byte-mapping scheme.
RXP
(4)
I 1 Serial differential port (FPGA external)
RXPOLARITY I 1 Similar to TXPOLARITY, but for RXN and RXP. When de-asserted,
assumes regular polarity. When asserted, reverses polarity.
RXREALIGN O 1 Signal from the PMA denoting that the byte alignment with the serial
data stream changed due to a comma detection. Asserted High when
alignment occurs.
RXRECCLK O 1 Clock recovered from the data stream by dividing its speed by 20.
RXRESET I 1 Synchronous RX system reset that “recenters” the receive elastic buffer.
It also resets 8B/10B decoder, comma detect, channel bonding, clock
correction logic, and other internal receive registers. It does not reset the
receiver PLL.
RXRUNDISP
(3)
O 1, 2, 4 Signals the running disparity (0 = negative, 1 = positive) in the received
serial data. If 8B/10B encoding is bypassed, it remains as the second bit
received (Bit “b”) of the 10-bit encoded data (see Figure 2-14, page 65).
RXUSRCLK I 1 Clock from a DCM or a BUFG that is used for reading the RX elastic
buffer. It also clocks CHBONDI and CHBONDO in and out of the
transceiver. Typically, the same as TXUSRCLK.
RXUSRCLK2 I 1 Clock output from a DCM that clocks the receiver data and status
between the transceiver and the FPGA core. Typically the same as
TXUSRCLK2. The relationship between RXUSRCLK and RXUSRCLK2
depends on the width of RXDATA.
TXBUFERR O 1 Provides status of the transmission FIFO. If asserted High, an
overflow/underflow has occurred. When this bit becomes set, it can
only be reset by asserting TXRESET.
TXBYPASS8B10B
(3)
I 1, 2, 4 This control signal determines whether the 8B/10B encoding is enabled
or bypassed. If the signal is asserted High, the encoding is bypassed.
This creates a 10-bit interface to the FPGA core. See the 8B/10B section
for more details.
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued)
Port I/O
Port
Size
Definition
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English