Xilinx RocketIO User Manual

52 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 2: Digital Design Considerations
R
--
signal GND : std_logic;
signal CLK0_W : std_logic;
signal CLK2X180_W : std_logic;
signal USRCLK2_M_W : std_logic;
signal USRCLK_M_W : std_logic;
begin
GND <= '0';
USRCLK2_M <= USRCLK2_M_W;
USRCLK_M <= USRCLK_M_W;
--
-- DCM Instantiation
U_DCM: DCM
port map (
CLKIN => REFCLK,
CLKFB => USRCLK_M,
DSSEN => GND,
PSINCDEC => GND,
PSEN => GND,
PSCLK => GND,
RST => RST,
CLK0 => CLK0_W,
CLK2X180 => CLK2X180_W,
LOCKED => LOCK
);
-- BUFG Instantiation
U_BUFG: IBUFG
port map (
I => REFCLKIN,
O => REFCLK
);
U2_BUFG: BUFG
port map (
I => CLK0_W,
O => USRCLK_M_W
);
U4_BUFG: BUFG
port map (
I => CLK2X180_W,
O => USRCLK2_M_W
);
end ONE_BYTE_CLK_arch;
Verilog Template
// Module: ONE_BYTE_CLK
// Description: Verilog Submodule
// DCM for 1-byte GT
// Device: Virtex-II Pro Family
module ONE_BYTE_CLK (
REFCLKIN,
REFCLK,
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English