Xilinx Zynq UltraScale+ ZCU208 - Page 46

User applicaons can change the output frequency of each SI570 within the range of 10 MHz to
810 MHz through the I2C1 bus interface. Power cycling the ZCU208 board reverts user clocks to
their default sengs.
These oscillators can also be reprogrammed from MSP430 system controller U38 (see TI
MSP430 System Controller on the Texas Instruments website for more system controller
informaon and the ZCU208 website for the ZCU208 System Controller GUI Tutorial (XTP_TBD).
DDR4 memory interface C0 (U47) and C1 (U130) SI570:
• Programmable oscillator: Silicon Labs Si570BAB001614DG (10 MHz-810 MHz, 300 MHz
default)
• I2C 0x5D
• LVDS dierenal output
• Total stability: 61.5 ppm
GTY SI570:
• Programmable oscillator: Silicon Labs Si570BAB000544DG (10 MHz-810 MHz, 156.250 MHz
default)
• I2C 0x5D
• LVDS dierenal output
• Total stability: 61.5 ppm
The SI5341B and SI570 data sheets can be found on the Silicon Labs website.
User SMA MGT Clock
[Figure 2, callout 34]
The ZCU208 board provides a pair of SMAs (J6, J7) for dierenal AC coupled user MGT clock
input into Zynq UltraScale+ RFSoC U1 GTY Bank 130. This dierenal signal pair is series-
capacitor coupled. The P-side SMA J6 signal USER_SMA_MGT_CLOCK_P is connected to U1
MGTREFCLK1P pin M34, and the N-side SMA J7 signal USER_SMA_MGT_CLOCK_N is
connected to U1 MGTREFCLK1N pin M35. The user SMA MGT clock dierenal signal
amplitude must not exceed -0.5V (Min) to 1.30V (Max).
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU208 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
zSFP/zSFP+ Module Connectors
[Figure 2, callout 15]
Chapter 3: Board Component Descriptions
UG1410 (v1.0) July 8, 2020 www.xilinx.com
ZCU208 Board User Guide 46
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