ABB REL670 2.2 IEC - Page 383

( )
1
= × -
M F L C
U I j X X
EQUATION1901 V1 EN-US (Equation 361)
en06000605.vsd
~
Z<
XS
X
L1
IF
U
U
M
Source
Fault voltage
Pre -fault voltage
X
C
Source voltage
U’
M
With bypassed
capacitor
With inserted
capacitor
F
IEC06000605 V1 EN-US
Figure 199: Voltage inversion on series compensated line
en06000606.vsd
I
F
U
S
U
’
M
=
x
U
L
x
U
S
I
F
x
U
L
U
S
x
U
C
U
M
x
U
S
With bypassed
capacitor
With inserted
capacitor
IEC06000606 V1 EN-US
Figure 200: Phasor diagrams of currents and voltages for the bypassed and
inserted series capacitor during voltage inversion
It is obvious that voltage U
M
will lead the fault current I
F
as long as X
L1
> X
C
. This
situation corresponds, from the directionality point of view, to fault conditions on
line without series capacitor. Voltage U
M
in IED point will lag the fault current I
F
in case when:
L1 C S L1
X X X X< < +
EQUATION1902 V1 EN-US (Equation 362)
Where
X
S
is the source impedance behind the IED
1MRK 506 369-UEN B Section 8
Impedance protection
Line distance protection REL670 2.2 IEC 377
Application manual