Abov MC96F6432Q User Manual

MC96F6432
102 June 22, 2018 Ver. 2.9
10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1)
The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) are set to ‘1’
when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine
is executed. Alternatively, the flag can be cleared by writing ‘0’ to it.
10.12.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1)
The external interrupt polarity 0 high/low register (EIPOL0H/L) and external interrupt polarity 1 register (EIPOL1)
determines which type of rising/falling/both edge interrupt. Initially, default value is no interrupt at any edge.

Abov MC96F6432Q Specifications

General

Brand	Abov
Model	MC96F6432Q
Category	Microcontrollers
Language	English