Abov MC96F6432Q User Manual

MC96F6432
June 22, 2018 Ver. 2.9 129
11.5.6 Register Map
Table 11-6 Timer 0 Register Map
Name
Address
Dir
Default
Description
T0CNT
B3H
R
00H
Timer 0 Counter Register
T0DR
B4H
R/W
FFH
Timer 0 Data Register
T0CDR
B4H
R
00H
Timer 0 Capture Data Register
T0CR
B2H
R/W
00H
Timer 0 Control Register
11.5.6.1 Timer/Counter 0 Register Description
The timer/counter 0 register consists of timer 0 counter register (T0CNT), timer 0 data register (T0DR), timer 0
capture data register (T0CDR), and timer 0 control register (T0CR). T0IFR and T0OVIFR bits are in the external
interrupt flag 1 register (EIFLAG1).
11.5.6.2 Register Description for Timer/Counter 0
T0CNT (Timer 0 Counter Register) : B3H
7
6
5
4
3
2
1
0
T0CNT7
T0CNT6
T0CNT5
T0CNT4
T0CNT3
T0CNT2
T0CNT1
T0CNT0
R
R
R
R
R
R
R
R
Initial value : 00H
T0CNT[7:0]
T0 Counter
T0DR (Timer 0 Data Register) : B4H
7
6
5
4
3
2
1
0
T0DR7
T0DR6
T0DR5
T0DR4
T0DR3
T0DR2
T0DR1
T0DR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : FFH
T0DR[7:0]
T0 Data
T0CDR (Timer 0 Capture Data Register: Read Case, Capture mode only) : B4H
7
6
5
4
3
2
1
0
T0CDR7
T0CDR6
T0CDR5
T0CDR4
T0CDR3
T0CDR2
T0CDR1
T0CDR0
R
R
R
R
R
R
R
R
Initial value : 00H
T0CDR[7:0]
T0 Capture Data

Abov MC96F6432Q Specifications

General

Brand	Abov
Model	MC96F6432Q
Category	Microcontrollers
Language	English