Abov A96G174 - User Manual

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Overview

Function Description
Important Technical Specifications
Usage Features
Maintenance Features

The A96G174/A96S174 is an advanced CMOS 8-bit microcontroller with 8 Kbytes of FLASH memory, designed to provide a highly flexible and cost-effective solution for various embedded control applications. It is based on the Mentor Graphics M8051EW core, which offers improved code efficiency and high performance.

Function Description

The microcontroller features an 8-bit CISC core (M8051, 2 clocks per cycle) and supports up to 14 peripheral interrupts, including EINT0 to EINT2, PCI (Pin Change Interrupt), three Timers (0/1/2), Watchdog Timer (WDT), Basic Interval Timer (BIT), USART Rx/Tx, I2C, ADC, and LVI (Low Voltage Indicator).

Memory organization includes 8 Kbytes of FLASH with self-read and write capability, 256 bytes of IRAM, and 256 bytes of XRAM. The FLASH memory supports in-system programming (ISP) and has an endurance of 30,000 times. The 16-bit program counter can address up to 64 Kbytes, but the device has 8 Kbytes of program memory space, including the Interrupt Vector Region. Data memory is divided into lower 128 bytes, upper 128 bytes, and SFR (Special Function Register) space. The lower 128 bytes are accessible by direct or indirect addressing, while the upper 128 bytes are only accessible by indirect addressing. SFRs are memory-mapped into Direct Memory at addresses between 80h and FFh.

Programmable pulse generation capabilities include pulse generation by Timers 1 and 2, 8-bit PWM by Timer 0, and 16-bit Complementary PWM by Timer 1 with Dead Time control.

The device also integrates a 12-bit A/D converter with 15 input channels.

Important Technical Specifications

CPU Core: 8-bit CISC (M8051, 2 clocks per cycle).
Memory:
- FLASH: 8 Kbytes (self-read/write, ISP, 30,000 endurance cycles).
- IRAM: 256 bytes.
- XRAM: 256 bytes.
Interrupts: Up to 14 peripheral interrupts, including 3 external interrupts (EINT0-2), 1 Pin Change Interrupt (PCI), 3 Timers (0/1/2), 1 Watchdog Timer (WDT), 1 Basic Interval Timer (BIT), 2 USART Rx/Tx, 1 I2C, 1 ADC, and 1 LVI.
Timers/Counters:
- Basic Interval Timer (BIT): 8-bit, 1 channel.
- Window Watch Dog Timer (WWDT): 8-bit, 1 channel.
- Timer 0: 8-bit, 1 channel (Timer/Counter, PWM, Capture modes).
- Timer 1: 16-bit, 1 channel (Timer/Counter, Capture, PPG, Complementary PWM modes).
- Timer 2: 16-bit, 1 channel (Timer/Counter, Capture, PPG modes).
Programmable Pulse Generation: Pulse generation (T1/T2), 8-bit PWM (T0), 16-bit Complementary PWM (T1, Dead time).
Minimum Instruction Execution Time: 125 ns (@ 16 MHz main clock), 61 µs (@ 32.768 kHz sub clock).
Power Down Modes: STOP mode, IDLE mode.
General Purpose I/O (GPIO): 18 ports.
Reset:
- Power-on reset: Reset release level 1.32V.
- Low voltage reset: 5 levels detect (1.61V, 1.77V, 2.13V, 2.46V, 3.56V).
Low Voltage Indicator: 3 levels detect (1.77V, 2.13V, 2.46V, 3.56V).
Communication Functions:
- USART: 8-bit USART x 1-ch or 8-bit SPI x 1-ch, Receiver timer out (RTO), 0% error baud rate.
- I2C: Compatible with I2C bus standard, Up to 400 kHz.
Internal RC Oscillator:
- HSIRC: 32 MHz (±1.5% @ 0~+50°C, ±2.0% @ -10~+70°C, ±2.5% @ -40~+85°C, ±5.0% @ -40~+105°C).
- LSIRC: 128 kHz (±20% @ -40~+85°C, ±30% @ -40~+105°C).
Operating Voltage and Frequency: 1.8V to 5.5V @ 32.768 kHz with crystal, 1.8V to 5.5V @ 0.5 MHz to 16.0 MHz with internal RC.
Operating Temperature: -40°C to +85°C, -40°C to 105°C.
Packages: Pb-free packages, 20 SOP / TSSOP / QFN, 16 SOPN.

Usage Features

I/O Ports: 3 groups of I/O ports (P0-P2) that can be configured as input/output, internal pull-up, and open-drain. P0 also supports interrupt signal generation. All I/O ports support debounce function with configurable clock sources (fx/1, fx/4, fx/4096).
Interrupt Controller: Supports a four-level priority scheme for maskable interrupts, with 2 groups of priority. Higher priority interrupts are served first. Default is level-trigger mode, but edge-trigger mode is also possible.
Clock Generator: Produces basic clock pulses for CPU and peripherals. Default system clock is 16 MHz from HSIRC OSC/2. Internal LSIRC oscillator (128 kHz) is recommended for stabilization on POR.
Basic Interval Timer (BIT): Free-running 8-bit timer for watchdog timer counting and basic interval timer interrupts. Provides stable clock generation during power-on and when exiting Stop mode.
Watchdog Timer (WDT): Detects CPU malfunctions and can generate a CPU reset or interrupt. Configurable overflow time and window open period (50%, 75%, 100%). Operates on a 4 kHz clock derived from the 128 kHz LSIRC.
Timers 0/1/2:
- Timer 0 (8-bit): Supports timer/counter, PWM output, and capture modes. Clocked by internal or external sources with various prescaler division rates.
- Timer 1 (16-bit): Supports timer/counter, capture, PPG (one-shot and repeat), and complementary PWM modes. Clocked by internal or external sources with various prescaler division rates.
- Timer 2 (16-bit): Supports timer/counter, capture, and PPG (one-shot and repeat) modes. Clocked by internal or Timer 1 A Match signal with various prescaler division rates.
12-bit ADC: Converts analog input signals to 12-bit digital values. Conversion requires 4 steps per bit and 12 setup clocks, totaling 60 clocks. Minimum conversion time is 7.5 µs.
I2C: Supports multi-master operation, 7-bit addressing, and bus busy detection. Data transfer up to 400 kHz.
USART: Supports full duplex, asynchronous/synchronous, master/slave SPI operation (all four modes), LSB/MSB first data transfer, high resolution baud rate generation, and various serial frame formats (5,6,7,8, or 9 data bits with 1 or 2 stop bits). Includes parity generation/checking, data overrun, framing error detection, and digital low pass filter. Supports 0% error baud rate using floating point counter logic.
Power Down Operation: IDLE mode keeps internal oscillation circuits active and peripherals operating, while CPU stops. STOP mode stops the selected oscillator, system clock, and peripheral clock, but retains RAM and control registers. Both modes can be released by reset or interrupts.
Reset: Five types of reset sources: External RESETB, Power ON RESET (POR), WDT Overflow Reset, Low Voltage Reset, and OCD Reset.

Maintenance Features

In-System Programming (ISP): The FLASH memory supports ISP, allowing the program to be written, erased, and overwritten while mounted on the board using a two-wire interface.
Debug Mode: The M8051EW core offers a Debug Mode with dedicated debug signals for external debug hardware (OCD and OCD II). This provides start/stop program execution, single-step operation, and program execution tracing.
OCD (On-Chip Debugger): ABOV's own interface for debugging, monitoring, and controlling the core, as well as external memory and devices. Supports memory monitoring and break functions.
- OCD 1 (96-Series): Basic debug operations (Run, Stop, Step, Break point, register/memory/SFR reading/writing).
- OCD 2 (94-Series, 97-Series): Extends OCD 1 features with Real-Time Monitoring (RTM) for CODE, XDATA, and IDATA, Run Flag support for emulation time measurement, and RAM Break support for IDATA, SFR, and XDATA.
Programmers: E-PGM+ USB (single programmer) and E-Gang4/6 (gang programmers for mass production) are available for programming.
Circuit Design Guide: Provides recommendations for PCB design for on-board programming, including resistor values (4.7 kΩ for DSCL and DSDA) and capacitive load limits (less than 100 pF) to ensure reliable communication in Debug mode.
Compiler Compatibility: Compatible with standard 8051 compilers due to the M8051EW core.